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Chapter 5

Shell-Level Commands
The shell-level commands for QuickHDL allow you to perform tasks such as 
creating and manipulating the contents of a design library, compiling source code, 
and invoking the QuickHDL simulator on a design unit. These commands are 
entered from the shell command line and are case-sensitive.

Notation Conventions for Shell 

Commands
The syntax elements of QuickHDL shell commands are signified as follows:
< >Angle brackets surrounding a syntax item indicate a user-defined 
option. Do not enter the brackets in commands.
[ ]Square brackets indicate an optional item. If the brackets surround 
several words, all must be entered as a group. The brackets are not 
entered.
¼An ellipsis indicates items that may appear more than once. The 
ellipsis itself does not appear in commands.
|The vertical bar indicates a choice between items on either side of 
it. Do not include the bar in the command.
monospaced type
Monospaced type is used in examples. 
Neither the prompt at the beginning of a line nor the <Enter> or <Return> key that 
ends a line is shown in the examples. 

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makefile_conv
The makefile_conv command is used to convert makefiles that were generated by 
qhmake (from QuickVHDL, V8.4_1 or earlier) to use the new library format.

Usage
makefile_conv [input] [output]

Arguments
If you do not specify optional arguments, makefile_conv will read from standard 
in and write to standard out. 

See also
qhmake

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qhdel
The qhdel command deletes a design unit from a specified library.

Usage
qhdel [ ±help ] [±lib <library_name> ][ ±verbose ]  <primary_design_unit> 
[ <secondary_design_unit> ]

Options
-±help
Displays a list of command options. 
-±lib <library_name>
Specifies the logical pathname of the library that holds the design unit to be 
deleted. Optional; by default, the design unit is deleted from the work library.
-±verbose
Displays progress message. Optional.

Arguments
-<primary_design_unit>
Specifies the name of an entity, package, configuration, or module to be 
deleted. Required.
-<secondary_design_unit>
Specifies the name of an architecture to be deleted. Optional; if omitted, all of 
the architectures for a specified entity are deleted. Invalid for a configuration, 
package, or module.

Examples
qhdel xor
Deletes the entity named xor and all its architectures.
qhdel xor behavior

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Deletes the architecture named behavior of the entity xor.

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qhdir
The qhdir command selectively lists the contents of a library.

Usage
qhdir [ -help ] [ L ] [ ±lib <library_name> ] [ <primary_design_unit> ]

Options
-±help
Displays a list of command options. 
--L
Lists a long description of each design unit listed.
-±lib <library_name>
Specifies the logical name or the pathname of the library to be listed. Optional; 
by default, the contents of the work library are listed.

Argument
-<primary_design_unit>
Specifies the name of a module or an entity whose architectures are to be 
listed. Optional; by default, all entities, configurations, and packages in the 
specified library are listed. 

Examples
qhdir ±lib design my_asic
Lists the architectures associated with the entity named my_asic that resides in the 
design library called design. 

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qhgencomp
The qhgencomp command extracts the interface to a Verilog module that has 
been compiled into a component library and creates a VHDL component 
declaration. This allows referencing the Verilog component from a VHDL design. 
The component declaration is written to stdout. 

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A Verilog module must be compiled before a VHDL component 
can reference it. The qhgencomp command only generates a 
VHDL componentÐyou still must perform any required 
compilation on both Verilog and VHDL source code. 

Syntax
qhgencomp [ -help ] [ -lib_name ] [ -s ] [ -b ] [ -v ] module_name 

Options
-±help
Displays a list of command options with a brief description for each. 
--lib_name
Library name (default is work).
--s
Generate std_logic port types (default).
--b
Generate bit port types.
--v
Generate vl_logic port types. 

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Argument
-<module_name>
Name of the module containing the component. 

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Examples
This example uses a Verilog module that is compiled into the work library. The 
module begins as Verilog source code
module top(i1, o1, o2, io1);
parameter width = 8;
parameter delay = 4.5;
parameter filename = "file.in";
input i1;
output [7:0] o1;
output [4:7] o2;
inout [width-1:0] io1;
endmodule
After compiling, qhgencomp is invoked on the compiled module:
qhgencomp top
and writes the following to stdout:
component top
generic(
width: integer := 8;
delay: real:= 4.500000;
filename: string:= "file.in"
);
port(
i1: instd_logic
o1: outstd_logic_vector(7 downto 0);
o2: outstd_logic_vector(4 to 7);
io1: inoutstd_logic_vector
);
end component;

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qhlib
The qhlib command creates a VHDL or Verilog design library.

Usage
qhlib [ -help ] [ ±dos ] <directory_name>

Option
-±help
Displays a list of command options. 
-±dos
Specifies that subdirectories in a library have names that are compatible with 
DOS. The option is not recommended if you use the qhmake utility. Optional.

Argument
-<directory_name>
Specifies the pathname of the library to be created. Required.

Examples
qhlib design
Creates a design library called design. You can define a logical name for the 
library using the qhmap command or by adding a line to the library section of the 
quickhdl.ini file that is located in the same directory.
The qhlib command must be used to create a library directory. Operating system 
commands cannot be used to create a library directory or index file.
If the specified library already exists as a valid QuickHDL library, the qhlib 
command will exit with an error message without touching the library.

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qhmake
The qhmake utility allows you to use the UNIX make program to maintain 
VHDL or Verilog libraries. The qhmake utility prints a makefile for a library to 
the standard output.

Usage
qhmake [ -help ] [ <library_name> ]

Argument
-±help
Displays a list of command options. 
-<library_name>
Specifies the library name; if none is specified, then work is assumed. 
Optional.

Examples
qhmake > makefile
Produces a makefile for library work.
qhmake ieee | make ±f ±
Pipes a makefile for library ieee into the make command.

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qhmap
The qhmap command defines a mapping between a logical library name and a 
directory by modifying the quickhdl.ini file. It also can be used to display all 
known mappings or just the current mapping of a specified logical name.

Usage
qhmap [ -help ] [-c] [-del] [<logical_name>]  [<path>]

Arguments
-±help
Displays a list of command options. 
-±c
Copies a quickhdl.ini file from the previous hierarchy of the default search 
path for .ini files into your current directory.
-±del
Deletes reference to the specified library. 
-<logical_name>
Specifies the logical name of the library to be mapped or deleted from the map. 
Optional.
-<path>
Specifies the pathname of the directory to which the library is to be mapped. 
Optional. If omitted, the command displays the mapping of the specified 
logical name.

Examples
qhmap design /my_sys/designs/wrg101
Establishes the logical library name design and maps it to the directory 
/my_sys/designs/wrg101.

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qhmap
Without any arguments, the qhmap command displays all current mappings 
(based on the contents of the current project file, the quickhdl.ini file).
qhmap my_asic
If just a logical name is given, the qhmap command will display the current 
mapping for that name if one exists.
qhmap -del old_asic
Used with the -del option, qhmap deletes a mapping from the current project.

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qhsim
You can use the qhsim command either to invoke the simulator or to view results 
of a previous simulation run (with the ±view option). 
When invoking the simulator, you can specify a design unit (configuration, 
entity/architecture pair, or module) for simulation. If you specify a configuration, 
it is invalid to specify an architecture. If you do not specify a design unit, the 
Simulation Startup dialog will appear and prompt you for one.

Usage
qhsim   [ ±help ] [ ±c ] [ -do ª<command_string>º | <macro_filename> ] [ ±i ] 
[ ±t <time_unit> ] [ ±gName=<value> ] [ ±GName=<value> ] 
[ ±lib <library_name> ] [ ±wav <filename> ] [ ±view <filename> ] 
[ -f <func> <file> ] [ ±file <filename> ] [ -nocompress ] [ -restore ]
[ ±noglitch ] [ ±noschematic ] [ ±schematic ] [ ±notcl ] [ -vital2.2b ]
[ ±sdfmin [<region>= ] <filename> ] [ ±sdftyp [<region>= ] <filename> ] 
[ ±sdfmax [<region>= ] <filename> ] [ ±sdfnowarn ] [ ±sdfholdv3 ]
[-treefont <fontname>] [ ±L <library_name> ] [ ±hazards ] 
[ +mindelays | +typdelays | +maxdelays ] [ +notimingchecks ] 
[ +<plusarg> ] [ ±usage ] [ ±version ] [ ±lmc ] [ ±title <window_name> ] 
[ +pulse_r/<percent> ] [ +pulse_e/<percent> ] [ -pwrvh ] [ -pwrvl ]
[ -multisource_delay <option> ] [ -vcdread <filename> ] 
[ -trace_foreign <int> ] <configuration | entity/architecture | module> 

Options
-±c
Run the simulator in command line mode. Optional. If used, must be the first 
option. See additional discussion in the examples. 
-±do ª<command_string>º | <macro_filename>
Instructs the simulator to use the command or macro specified by 
<command_string> or the macro file named by <macro_filename> rather than 
the startup file specified in the .ini file, if any. 

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-±i
Run the simulator in interactive mode. Optional. If used, must be the first 
option. See additional discussion in the examples.
-±t <time_unit>
Specifies the simulation time resolution. Optional. If omitted, the value 
specified in the quickhdl.ini file will be used; <time_unit> must be one of: fs, 
ps, ns, us, ms, sec, min, hr. NOTE: The maximum available simulation time 
is 2**63 simulation cycles.
-±g Name=<generic_value>
Specifies a value for a top-level generic parameter. Optional. If you are 
simulating an entity that has one or more generic parameters, you may specify 
their values using the syntax:
-g Name=value
Name is the name of the generic parameter, exactly as it appears in the VHDL 
source (case is ignored). Value is an appropriate value for the declared data 
type of the generic parameter. No spaces are allowed anywhere in the 
specification, except within quotes when specifying a string value. Multiple ±g 
options are allowed, one for each generic parameter.
-±G Name=<generic_value>
Override the value of generic parameter. Optional. If you are simulating an 
entity that has one or more generic parameters, you may specify their values 
using the syntax:
-G Name=value
Name is the name of the generic parameter, exactly as it appears in the VHDL 
source (case is ignored). Value is an appropriate value for the declared data 
type of the generic parameter. No spaces are allowed anywhere in the 
specification, except within quotes when specifying a string value. Multiple -G 
options are allowed, one for each generic parameter. 
-±lib <library_name>
Specifies the name of the library in which the design unit resides. Optional; if 
omitted, the work library is used.

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·±wav <filename>
Specifies the name of the QuickHDL signal log file to create. The default is 
vsim.wav. Optional. See additional discussion in examples.
-±view <filename>
Specifies a log file (filename) for the simulator to read. Allows you to use the 
simulator to view the results from an earlier simulation. The Structure, Signals, 
Waveform, and List windows can be opened to look at the results stored in the 
log file. See additional discussion in Examples.
-±f <fcn_name> <c_lib>
Loads the foreign module named fcn_name from library c_lib. You must use 
the -noschematic option in conjunction with -f to be able load the fcn_name 
module. Using the -f option to load a foreign module disables the ability to edit 
and compile source code within a QuickHDL simulation session, along with 
Schematic source view capability (see Table 5-1). 
--file <filename>
Specifies a file with more command line arguments. Allows complex 
arguments to be reused without retyping.
--nocompress
See the -restore option.
--restore <filename> [ -nocompress ]
Specifies that qhsim restores a simulation saved with the checkpoint command. 
Use the -nocompress switch if compress was turned off during the checkpoint 
command.
-±noglitch
Disable glitch generation (provided for VITAL). 

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-±noschematic
Disables Schematic source view capability, along with the ability to edit and 
compile source code within a QuickHDL simulation session. Enables the use 
of -f option, along with checkpoint and restore commands (see Table 5-1). 
-±schematic
Enables Schematic source view capability, along with the ability to edit and 
compile source code within a QuickHDL simulation session. Disables the use 
of -f option, along with checkpoint and restore commands (see Table 5-1). 
-±notcl
Specifies that the simulator is to be run without Tcl commands, which provides 
compatibility with earlier releases. Optional. See Appendixes E and F for more 
information about Tcl.
--vital2.2b
Select SDF mapping for VITAL 2.2b (default is VITAL 95).
-±sdfmin [<region>=] <filename>
Selects minimum timing from the specified SDF (standard delay format) file. 
Optional. See additional discussion in the examples.
-±sdftyp [<region>=] <filename>
Selects typical timing from the specified SDF (standard delay format) file. 
Optional.
-±sdfmax [<region>=] <filename>
Selects maximum timing from the specified SDF (standard delay format) file. 
Optional. 
-±sdfnowarn
Disables warnings from the SDF reader.

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-±sdfholdv3
Change the SDF mapping for HOLD to comply with VITAL 95: 
thold_<data>_<clock>. 
--treefont <fontname>
Specifies the X Windows font to be used by the simulator in all ªtreeº 
windows. Optional. If omitted, the simulator uses the fonts specified by the 
X Windows defaults file.
-±L <library_name>
Search library_name for design units instantiated by Verilog. 
-±hazards
Enables hazard checking in Verilog modules. 
-+mindelays | +typdelays | +maxdelays
By default, qhsim selects typical delays from the Verilog min:typ:max 
expressions. You can explicitly select the delay set by invoking qhsim with the 
+mindelays, +typdelays, or +maxdelays options. For example, the following 
simulates a module named topmod with maximum delays:
qhsim +maxdelays topmod
-+notimingchecks
Disable all timing checks done in Verilog specify blocks. 
-+plusarg
Make plusarg accessible to the Verilog PLI when using the 
mc_scan_plusargs routine. 
-±help
Displays a list of command options with a brief description for each. 
-±usage
Displays a list of command options with a brief description for each. 

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-±version
Displays the QuickHDL version number. 
-±lmc
Enables support for Swift models from Logic Modeling Corporation. This 
option is required only for SunOS 4.1.xÐSwift models are supported on other 
platforms without using this option. 
-±title <window_name>
Specifies window_name as the title for the main QuickHDL window. Optional. 
-+pulse_r/<percent>
Sets the module path pulse rejection limit as a percentage of the path delay.
-+pulse_e/<percent>
Sets the module path pulse error limit as a percentage of the path delay.
--pwrvh
Enables the QuickPower application to be used with QuickHDL-VHDL
--pwrvl
Enables QuickPower application to use with QuickHDL-Verilog.
--multisource_delay <sdf_option>
Applies a delay of <sdf_option> (Verilog only) which is one of the following:
   max 
   min 
   latest 
--vcdread <filename>
Simulates the VHDL top-level design from the specified VCD file. Optional.
The VCD file must have been created in a previous simulation using the 
vcd_file -nomap -direction command.

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--trace_foreign <int>
Creates two kinds of foreign interface traces: a log of the functions that were 
called (with the value of the arguments and the results returned); and a set of 
C-language files to replay the C-language.
<int> can be one of the following:
1 - create log only (writes a local file called ªmti_traceº)
2 - create replay only (writes local files called ªmti_data.cº).
3 - create both log and replay objects
4 - use for replaying the original actions.

Arguments
-<configuration>
Specifies the name of a top-level configuration to be simulated. Optional. 
-<entity>
Specifies the name of a top-level VHDL entity to be simulated. Optional. 
-<architecture>
Specifies the name of a VHDL architecture to be simulated. Optional; if 
omitted the last architecture compiled for the specified entity is simulated. 
Invalid if a configuration is specified. 
-<module>
Specifies the name of a Verilog module to be simulated. Optional. 

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Examples
qhsim ±lib design my_asic structure
Invokes the simulator on the entity my_asic and the architecture structure, which 
have been compiled in the library named design.
 qhsim ±lib -treefont zapfdingbats design my_asic structure
Invokes the simulator as shown in the preceding example and specifies the 
ZapfDingbats font to be used in tree windows. 
 qhsim ±g edge="low high" ±g VCC=4.75 cpu
Invokes the simulator on the entity cpu and uses the -g option twice to assign 
values to generic parameters edge and VCC. 
qhsim ±view my_design.i03
Instructs the simulator to view the results of a previous simulation run stored in 
the log file, my_design.i03. 
Use the -wave option to specify the name of the signal log file to create if you plan 
to create many files for later viewing. This is also important for concurrent 
invocation in the same design directory, since, if not used, each qhsim attempts to 
create the same qhsim.wav file, a contention problem. For example:
qhsim -lib design my_asic structure -wave my_design.i01
qhsim -lib design my_asic structure -wave my_design.i02
qhsim -lib design my_asic structure -sdfmin asic.sdf -sdfnowarn
Invoke the simulator using the minimum timing from the SDF file asic.sdf. In 
addition, the SDF reader's warnings are turned off. When annotating a Verilog 
design, the <region> option is the module instance to be annotated. For example, 
to annotate top.ui with minimum timing from the SDF file named mysdf:
qhsim -sdfmin /u1=mysdf top

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Set VerilogNaming to 1 in the quickhdl.ini file if you choose to use Verilog style 
pathnaming for <region>:
qhsim -sdfmin top.u1=mysdf top
The -multisource_delay option controls how multiple PORT or 
INTERCONNECT constructs that terminate at the same port are handled. By 
default, the Module Input Port Delay (MIPD) is set to the latest value encountered 
in the SDF file. You may also choose the min or max of the values.
This example searches the libraries gatelib, mylib, and work. Qhsim looks for 
design units in libraries specified with the -L option. The libraries are searched in 
the order they are presented on the command line. If -L options are not used, or if 
a design unit is not found, then qhsim searches the work library.

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Additional Information 
As indicated in the ªOptionsº section above, the -f, -schematic, and -noschematic 
options to the qhsim command interact with each other. These options also affect 
the availability of the checkpoint and restore commands, along with the ability to 
edit and compile source code within a QuickHDL simulation session. 
Table 5-1 summarizes interactions among the -f, -noschematic, and -schematic 
options for both the qvsim command (i.e., how they previously worked for 
QuickVHDL) and the qhsim command (i.e., how they presently work for 
QuickHDL). The default condition shows the effect of not specifying any of these 
options. 
Table 5-1. Summary of -f, -schematic, and -noschematic Options
Edit 
source?
Compile 
source?
Schematic
 source 
view?
-f option?
Checkpoint/
restore?
qvsim default 
Yes 
Yes 
Yes 
No 
No 
-schematic 
Yes 
Yes 
Yes 
No 
No 
-noschematic 
No 
No 
No 
Yes 
Yes 
qhsim default
Yes 
Yes 
No 
No 
Yes 
-schematic
Yes 
Yes 
Yes 
No 
No 
-noschematic
No 
No 
No 
Yes 
Yes 

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qvhcom
The qvhcom command is used to compile VHDL source code for simulation and 
add it as a design unit to a specified working library (or to the work library by 
default). 

Usage
qvhcom  [ ±help ] [ ±work <path> ] [ ±line <number> ] [ ±source ] [ ±nodebug ] 
[ ±quiet ] [ ±nologo ] [ ±s ] [ ±nowarn <number> ] [ ±nocheck ] 
[ ±no1164 ] [ ±novital [all | <fname>...] ] [ ±noaccel [<pname>...] ] 
[ ±explicit ] [ ±93 ] [ ±87 ] [ ±just eapbc ] [ ±skip eapbc ] [ -O0 ]
[ ±usage ] [ ±version ] [ ±synth ] [ ±nosynchk ] [ -refresh ] [ -O4 ]
[ -qhpro_syminfo ] [ -novitalcheck ] [ -f <path> ] <filename(s)> 

Options
-±help
Displays a list of command options with a brief description for each. 
-±work <path>
Specifies a logical name or pathname of a library that is to be mapped to the 
logical library work. Optional; by default, the compiled design units are added 
to the work library. The specified pathname overrides the pathname specified 
for work in the project file.
-±line <number>
Starts the compiler on the specified line in the VHDL source file. Optional; by 
default, the compiler starts at the beginning of the file.
-±source
Displays the associated line of source code before each error message that is 
generated during compilation. Optional; by default, only the error message is 
displayed.

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-±nodebug
Causes the compiler to compile models without generating line number 
information. Models so compiled do not use any of the QuickHDL debugging 
features. Note that this is not a speed switch like the nodebug option on many 
other products. Optional. See additional discussion in the Examples section.
-±quiet
Disables messages while loading. Optional. 
-±nologo
Suppresses the copyright banner during compilation. Optional.
-±s
Instructs the compiler not to load the standard package. Optional. This option 
should only be used if you are compiling the standard package itself.
-±nowarn <number>
Selectively disables an individual warning message. Optional. Multiple 
-nowarn options are allowed. Warnings may be disabled for all compiles via 
the quickhdl.ini file.
The warning message numbers are:
 1 unbound component
 2 process without a wait statement
 3 null range
 4 no space in time literal
 5 multiple drivers on unresolved signal
-±nocheck
Disables run time range checking. In some designs, this could result in 2X 
speed increase. Optional.
-±novitalcheck
Disables Vital95 compliance checking if you are using Vital 2.2b. Optional.

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-±no1164
Causes the source files to be compiled without taking advantage of the built-in 
version of the IEEE std_logic_1164 package. Optional. This will typically 
result in longer simulation times for VHDL programs which use variables and 
signals of type std_logic.
-±novital ALL
Causes qvhcom to use your VHDL code for VITAL procedures rather than the 
accelerated and optimized timing and primitive packages built into the 
simulator kernel. Optional.
-±novital [ALL | <fname>...] 
Disables optimization for VITAL function fname (all VITAL functions if 
fname is all)
-±noaccel [<pname>...] 
Disables optimization for package pname. For example, 
noaccel numeric_std turns off acceleration for the numeric_std package 
located in the ieee library.
-±explicit
Used to ignore an error in packages supplied by some other EDA vendors; 
directs the compiler to resolve ambiguous function overloading in favor of the 
explicit function definition. See additional discussion in the Examples section.
-±93
Specifies that the simulator is to support VHDL 1076-1993. Optional. If used, 
must be the first option. See additional discussion in the Examples section.
-±87
Disables support for VHDL 1076-1993. This is the qvhcom default. Optional. 
If used, must be the first option. See additional discussion in the Examples 
section.

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-±O0
(letter ªOº zero) Lowers the optimization level to minimum. Optional.
-±O4
(letter ªOº four) Enables standard optimization. Default.
-±just eapbc
Directs the complier to ªjustº include:
e - design entities
a - architectures
p - packages
b - package bodies
c - configurations
Any combination can be used, but one choice is required if you use this 
command option.
-±skip eapbc
Directs the compiler to skip all:
e - design entities
a - architectures
p - packages
b - package bodies
c - configurations
Any combination can be used, but one choice is required if you use this 
command option.
-±usage
Displays a list of command options with a brief description for each. 
-±version
Prints version information only. 

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-±synth
Compile VHDL code for synthesis by Autologic II. This is done by generating 
dependency files, breaking the VHDL code into separate entity and 
architecture files, and then running the language parser to check for potential 
problems with synthesizable code. Optional. 
-±nosynchk
Compile VHDL code for synthesis by Autologic II, but does not run the 
language parser to check for potential problems with synthesizable code. 
Optional. 
--refresh
Regenerates a library image. Optional. By default, the work library is updated; 
use -work <library> to update a different library. For design units compiled 
with v8.5_4.6 or later qvhcom, the design units are ªrecompiledº or updated to 
be compatible with the current qhsim.
Note: You cannot refresh design units that were compiled with a pre-v8.5_4.6 
compiler.
-±f <path>
Specifies pathname to file with additional command line arguments. Optional.
--qhpro_syminfo
In the v8.5_4.6 release of QuickHDL, qvhcom no longer created the 
_parsed.vhd file (seeªReleasing Models without Source Codeº on page G-6). 
This file is required to use the generate_symbol utility in Design Architect, 
necessary to place VHDL in a schematic design for QuickHDL Pro. This 
switch tells qvhcom to create the _parsed.vhd file during compilation.

Argument
-<filename>
Specifies the name of a file containing the VHDL source to be compiled. One 
filename is required; multiple filenames can be entered separated by spaces. 
No options can appear after filename(s) on the command line.

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Examples
qvhcom  example.vhd
The preceding example compiles the VHDL source code contained in the file 
example.vhd.
qvhcom ±87 o_units1 o_units2
qvhcom ±93 n_unit91 n_unit92
QuickHDL supports designs that use elements conforming to both the 1993 and 
the 1987 standards. Compile the design units separately using the appropriate 
switches as shown in the example. Note that in the example above, the ±87 switch 
on the first line is redundant since the default is to compile to the 1987 standard.
qvhcom ±nodebug example.vhd
You can use the ±nodebug switch to compile models that can be distributed 
without source code information. First, compile your code using the ±nodebug 
option as in the example above. 
Models compiled this way do not use any of the QuickHDL debugging features so 
the simulator will not be able to ªsee intoº the model. This also means that you 
cannot set breakpoints or single step within this code, so don't compile with this 
switch until you're sure you're done. 
For the last step, use a command like this one to remove the architecture and 
package bodies that are in the library:
rm <library>/*/*/<design_unit>.vhd
qvhcom -explicit example.vhd

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After compilation, there is a subdirectory in the QHSIM library for 
each primary design unit. For VHDL, these subdirectories contain 
a file named _parsed.vhd that contains the source code for that 
primary unit. Do not delete this fileÐit is used for the unit 
interface and the simulator cannot invoke without it. 
The preceding example uses the -explicit option. All enumeration data types in 
VHDL get an ªimplicitº definition for all the relational operators (=, /=, <, <=, >, 

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>=). Any of these implicit declarations can be hidden by an explicit declaration of 
a particular relational operator in the same package (IEEE Std 1076-1987, 
Standard VHDL Language Reference Manual, Section 10.3). However, if another 
version of the particular operator is declared in a different package than that 
containing the enumeration declaration, and both operators satisfy the same set of 
overloading rule checks, neither can be used without explicit naming. The 
following example assumes the = operator has been overloaded and needs to be 
called using explicit naming:
ARITHMETIC.º=º(left, right)
The -explicit option to the qvhcom command allows the explicit = operator to 
hide the implicit one. This option is provided to allow compatibility with other 
tools that do not implement the VHDL standard correctly. 
qvhcom -work mylib -refresh
The -work option specifies mylib as the library to regenerate. The -refresh option 
rebuilds the library image without using source code, allowing models delivered 
as compiled libraries without source code to be rebuilt for a specific release of 
QuickHDL (V8.5_4.6 or later only).
If your library contains Verilog design units, you must regenerate them using the 
qvlcom -refresh command. See ªAutomatically Regenerating Librariesº on 
page 2-6 for more information.

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qvlcom
The qvlcom command is used to compile Verilog source code for simulation and 
add it as a design unit to a specified working library (or to the work library by 
default). The qvlcom command is used just like qvhcom, except that you do not 
need to compile a Verilog module before it is referenced (unless the module is 
referenced from VHDL). 
Verilog modules and VHDL design units may be compiled into the same library. 
An instantiation from Verilog assumes that the instantiated module resides in the 
work library. You can use an extended form of instantiation to select a specific 
library. For example: 
\mylib.moda u1 (a, b, c);

Usage
qvlcom  [ ±help ] [ ±work <path> ] [ ±line <number> ] [ ±source ] [ ±nodebug ]
[ ±quiet ] [ ±nologo ] [ ±hazards ] [ ±v <path> ] [ ±y <path> ] [ -u ]
[ +libext+<suffix> ] [ +define+<macro_name> ] [ +incdir+<directory> ] 
[ ±usage ] [ ±version ] [ -93 ] [ -refresh ] <filename(s)>

Options
-±help
Displays a list of command options with a brief description for each. 
-±work <path>
Specifies a logical name or pathname of a library that is to be mapped to the 
logical library work. Optional; by default, the compiled design units are added 
to the work library. The specified pathname overrides the pathname specified 
for work in the project file.
-±line <number>
Starts the compiler on the specified line in the Verilog source file. Optional; by 
default, the compiler starts at the beginning of the file.
-±source
Print the source line with error messages. 

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-±nodebug
Do not put symbolic debugging information into library. 
-±quiet
Disable messages while loading. 
-±nologo
Suppresses the copyright banner during compilation. Optional.
-±hazards
Check for hazards at run-time. 
-±v <path>
Specifies a Verilog source library file. 
-±y <path>
Specifies a Verilog source library directory. 
-±u
Converts regular Verilog identifiers to uppercase. Allows case insensitivity for 
module names. Optional.
-+libtext+<suffix> 
Specify suffix of files in library directory. 
-+define+<macro_name> [=macro_text]
Same as the following compiler directive: 
Qdefine macro_name macro_text 
-+incdir+<directory> 
Search directory for files included with Qinclude filename. 
-±usage
Displays a list of command options with a brief description for each. 

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-±version
Prints version information only.
--93
Specifies that the VHDL interface to Verilog modules uses VHDL 1076-93 
extended identifiers to preserve case in Verilog identifiers that contain 
uppercase alphanumerics.
--refresh
Regenerates a library image. Optional. By default, the work library is updated; 
use -work <library> to update a different library. For design units compiled 
with v8.5_4.6 or later qvhcom, the design units are ªrecompiledº or updated to 
be compatible with the current qhsim.
Note: You cannot refresh design units that were compiled with a pre-v8.5_4.6 
compiler.

Argument
-<filename>
Specifies the name of a file containing the Verilog source to be compiled. One 
filename is required; multiple filenames can be entered separated by spaces. 
No options can appear after filename(s) on the command line. 

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Compiler directives
QuickHDL presently supports the following Verilog compiler directives for use 
with the qvlcom command:
-`default_nettype <net_type>
-`define <macro_name> <macro_text> 
-`delay_mode_distributed
-`delay_mode_path
-`delay_mode_unit
-`delay_mode_zero
-`else
-`endif
-`ifdef
-`include
-`nounconnected_drive
-`resetall
-`timescale
-`unconnected_drive
-`undef
-`uselib   (for details, see ªVerilog Quselib Compiler Directiveº on page 3-4)
The following Verilog compiler directives will be supported in a future release:
-`celldefine 
-`endcelldefine 

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Examples
qvlcom  example.vlg
The preceding example compiles the Verilog source code contained in the file 
example.vlg.
qvlcom ±quiet o_units1 o_units2 
qvlcom ±nodebug example.vlg
This example uses the ±nodebug switch to compile models that can be distributed 
without source code information. Models compiled this way do not use any of the 
QuickHDL debugging features so the simulator will not be able to ªseeº into the 
model. This also means that you cannot set breakpoints or single step within this 
code, so don't compile with this option until you're sure you're done. 
qvlcom top.v -v und1
After compiling top.v, qvlcom scans the file und1 for modules or primitives 
referenced but undefined in top.v. Only referenced definitions are compiled.
qvlcom -work mylib -refresh
The -work option specifies mylib as the library to regenerate. The -refresh option 
rebuilds the library image without using source code, allowing models delivered 
as compiled libraries without source code to be rebuilt for a specific release of 
QuickHDL (V8.5_4.6 or later only).
If your library contains VHDL design units, you must regenerate them using the 
qvhcom -refresh command. See ªAutomatically Regenerating Librariesº on 
page 2-6 for more information.

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tssi2mti
The tssi2mti command is used to convert a vector file in Summit Design Standard 
Events Format into a sequence of force and run commands. The stimulus is 
written to the standard output. 

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The source code for tss2mti is provided in the file tssi2mti.c in the 
examples directory. The source code must be compiled and the 
executable installed before using tss2mti.

Syntax
tssi2mti <signal_definition_file> [<sef_vector_file>]

Arguments
-signal_definition_file
Specifies the name of the Summit Design signal definition file describing the 
format and content of the vectors. Required.
-sef_vector_file
Specifies the name of the file containing vectors to be converted. If none is 
specified, standard input is used. Optional.

Examples
tssi2mti trigger.def trigger.sef > trigger.do
The command will produce a do file named trigger.do from the signal definition 
file trigger.def and the vector file trigger.sef.
tssi2mti trigger.def < trigger.sef > trigger.do
This example is exactly the same as the previous one, but uses the standard input 
instead.

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See also
force
run
write tssi
qhsim 

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wav2log 
This command translates a QuickHDL log file (vsim.wav) to a QuickSim II log 
file. The command reads the vsim.wav log file generated by the list, wave, or log 
commands in the simulator and converts it to the QuickSim II log file format. 

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You must exit QHSIM before running wav2log because vsim.wav 
(or other user-specified wave files) are updated dynamically. 

Syntax 
wav2log [ -input ] [ -output ] [ -inout ] [ -internal ] [ -l <level> ] [ -4.1 ] [ -4.3 ]
[ -4.4 ] [ -lower ] [ -quiet ] [ -help ] [ -o outfile ] <wavfile>

Options 
--input 
Lists only the input ports. This may be combined with the -output, -inout, or
-internal switches. 
--output 
Lists only the input ports. This may be combined with the -input, -inout, or
-internal switches. 
--inout 
Lists only the inout ports. This may be combined with the -input, -output,
or -internal switches. 
--internal 
Lists only the internal signals. This may be combined with the -input, -output,
or -inout switches. 
--l <level> 
Lists the signals at or below the specified level. 

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--4.1 
Reads older version (pre-4.2) .wav files. (Currently, files are version 4.4.) 
--4.3
Reads intermediate version (4.2 and 4.3) .wav files. (Currently, files are 
version 4.4.) 
--4.4
Reads version (4.4) .wav files. (Currently, files are version 4.6.) 
--lower
Uses signal names that are lower in the hierarchy.
--quiet 
Disables error message reporting.
-±help
Displays a list of command options with a brief description for each. 
--o outfile 
Directs the output to be written to the file specified by outfile. The default 
destination for the log file is standard out. 

Argument 
-<wavfile>
Specifies the QuickHDL log file that you are converting.

Additional Information
In some cases, the VHDL used in the original simulation generates states other 
than qsim_12state. The resulting waveform database (WDB) contains states that 
are surrounded by single quotes (e.g. `0' and `1'). To make your WDB compatible 
with QuickSim II models, you need to use a function named $convert_wdb(). 
This function was created to convert WDBs resulting from VHDL models using 
std_logic or std_ulogic. Other VHDL types such as qsim_state or bit (2 state) need 

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no conversion, as they are directly compatible with qsim_12state-compatible 
QuickSim II-compatible WDBs.
You can use the following procedure to convert a logfile or WDB to a 
QuickSim II-compatible WDB. This procedure shows how to convert the WDB in 
memory so that you do not have to save it to disk, as with the force files. 
1.Load the logfile or WDB into a WDB other than ªforces.º For example, a 
WDB named force_clk could be loaded as new_force_clk. The reason to 
load it as another name is that the utility replaces the WDB instead of 
copying it. If you later save the WDB without using ªSave As,º your 
original WDB would be lost. 
2.Type the following function call in a command prompt: 
$convert_wdb(ªnew_forces_clkº,0);
3.Perform a connect_wdb (either through the pulldown menus, the Connect 
WDB palette icon under Stimulus, or a function invocation). You specify 
the name of the WDB that you loaded. (In this case, new_forces_clk).
You can then issue a run command, and the stimulus in the converted WDB will 
be applied. The $convert_wdb() function converts the WDB named in the first 
argument to the type qsim_12state, so that QuickSim II models will accept it as 
stimulus. The second argument to $convert_wdb specifies the type of conversion 
(currently, only one type of conversion is supported). 

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