CURRICULUM VITA
Zainalabedin Navabi
Electrical and Computer Engineering
409 Dana Building
Northeastern University
Boston, MA 02115
(617) 373-3034 (Off) (617) 373-4159 (Msg) (617) 373-8970 (Fax) (617) 266-0121 (Res)
Email: navabi@ece.neu.edu
PERSONAL: Born August 20, 1952, Tehran, Iran Married, and two children
EDUCATION:
1978-1981:
Ph.D. in Electrical Engineering, University of Arizona, Tucson, Arizona 85721
Research: VLSI Design Automation Using A Hardware Programming Language
Minor: Computer Science
1975-1978:
M.S. in Electrical Engineering, University of Arizona, Tucson, Arizona 85721
Research: Digital System Simulation at the Register Transfer Level
Minor: Computer Science
1971-1975:
B.S. in Electrical Engineering, University of Texas, Austin, Texas 78712
Graduated With HIGHEST HONORS with Grade Point Average of 3.9
SPECIALIZATION:
Specialized in Hardware Description Languages, Digital System Simulation, VLSI Design Automation, Modeling, Hardware Generation, and Silicon Compilation. Have developed or directed development of programs for Register Transfer Level simulation, PAL fuse layout generator, Minimum complex gate implementation of digital circuits, behavioral and component synthesis, back annotation and extraction programs, HDL based tools, and RTL language based silicon compilers.
PROFESSIONAL AFFILIATIONS:
Institute of Electrical and Electronic Engineers (IEEE)
IEEE Computer Society
American Society of Engineering Education (ASEE)
European Association for Microprocessing and Microprogramming (EUROMICRO)
Association of Computing Machinery (ACM)
HONORS:
Graduated with HIGHEST HONORS, University of Texas at Austin, May '75.
Motorola Merit Scholarship Award, October 1981.
EXPERTISE:
Experienced in using various, workstations, minicomputers, super-mini and main frames. Proficient in many languages including FORTRAN, PASCAL, C-Language, and Basic. Familiar with ALGOL, SNOBOL, PL/1, LISP, PROLOG and several assembly languages. Experienced in interface design and computer graphics. Thorough understanding of digital system design, microprocessors, compiler design and language implementation, compiler-compilers, data structures, and operating systems, field programmable devices and related CAD tools, and custom and semi-custom VLSI chip design and CAD tools.
MAGAZINES:
"System Test:What, Why, and How?" A D&T Roundtable for the IEEE publication Design & Test of computers; August 1990; with Jack Arabian, Robert Rolfe, Muary Smeyne, Harold Carter, and Ernie Millham.
Z.Navabi and John Dube, "An Introduction to VHDL for Description of Digital systems, " Under Review for: The IEEE Potentials.
MANUALS and WORKBOOKS:
Z. Navabi and F. J. Hill, "User Manual for AHPL Simulator (HPSIM2)/AHPL Compiler (HPCOM)," Published by Engineering Experiment Station, University of Arizona, December 1, 1988.
Z. Navabi and John Sutter,"User Manual for OCT2HILO Program," Published by Massachusetts Microelectronics Center, Westboro MA, February 15 1991.
Z. Navabi, "Advanced VHDL for Hardware Design and Modeling," Published by Okura and Company Ltd. Tokyo, Japan October 1993.
BOOKS:
Z. Navabi, "VHDL: Analysis and Modeling of Digital System," . McGraw Hill Company, N.Y., New York.(1992)
Z. Navabi, "VHDL: Analysis and Modeling of Digital System,". McGraw Hill Company, N.Y., New York.(1997)
.
Japanese translation copyright ( 1994 by Nikkei BP Publishing Center, Inc.
PATENTS:
Z. Navabi, "Timed-State-Machines: A Representation for Analysis and Synthesis of Behavioral Descriptions," Patent Application Filed with Digital Equipment Corporation, July 1990.
PERIODICALS:
"Faculty Profile, Zainalabedin Navabi of N.U. Speaks Language of Computers, " Micro News, Publication of Massachusetts Microelectronics Center, Volume IV, Number 2, Fall 1990.
EQUIPMENT AND SOFTWARE GRANTS:
Workview Digital Design System: Negotiated a $228,000.00 software grant from the Viewlogic Incorporation. Software is now being used for the junior level digital design course.
Xilinx Programmable Device Design System: Negotiated donation of one Xilinx Design system ($22,000.00).
Workview Digital Design System: Negotiated a $1,316,000.00 software grant for DEC stations from the Viewlogic Incorporation. Software is now being used for the junior level digital design course.
CURRENT THESIS PROJECTS:
Alireza Khalafi, "Behavioral Test Simulation in Digital Circuits"
Parisa Najde-Samii, "Implementation of a testbench for 1149.1 boundry scan in VHDL"
SOFTWARE PROGRAMS DEVELOPED:
NUSYN: Synthesis program for generation of layout in CIF format from VHDL descriptions.
HPSIM2: Function level simulator for AHPL. This program has been installed on several main-frame, mini, and personal computers, and is being distributed by the University of Arizona. There are over 200 installations of this program at various universities and industrial sites.
OCT2HILO: A program for generating HILO hardware descriptions from OCT graphical front end. This program is being distributed by M2C. Reference: Micro News, Publication of Massachusetts Microelectronics Center, Volume IV, Number 2, Fall 1990.
VHDL CPU Model: Have developed model for a 32-bit CPU in VHDL. This model executes on SUN computers in the Intermetrics simulation environment. It has been made available to several researchers in the area of hardware description languages. Work on an NSF proposal for Software Capitalization Grant program for the distribution of this software is presently being conducted.
COMMITTEE ACTIVITIES:
Member of the Electrical and Computer Engineering, Graduate Affairs Committee, representing Computer Engineering; since 1987.
Member of the College of Engineering, Computer Advisory Committee, representing Electrical and Computer Engineering Department; since 1988.
Member of the University Computer Resources Center, Advisory Committee on Academic Computing (ACAC), representing college of Engineering; 1988-1990.