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Chapter 8

Simulator Command Dictionary
The simulator commands used to control the QuickHDL simulator are described 
in this section. These commands are valid only after loading a design by using the 
qhsim command or the graphical interface. The commands here are entered either 
in macro files or on the command line of the main window and are not 
case-sensitive. The commands are also automatically entered on the command 
line when you use the graphical user interface of the QuickHDL simulator. 
Note that in addition to the commands documented in this section, you can add the 
Tcl commands described in Appendices E and F. A qhsim command switch 
determines which set of commands is enabled. The larger set Ð all those in this 
section plus the Tcl commands Ð is the default.
Appendix G, Tips and Techniques, gives additional information on using several 
of the commands in this section. This additional information is referenced from 
the ªSee alsoº section of these commands.
The subsections below describe the notation conventions for the commands. 
Following this are detailed descriptions of each command in alphabetical order by 
command name.

Notation Conventions
The syntax elements of the commands are signified as follows: 
<  >Angled brackets surrounding a syntax item indicate a user-defined 
argument. Do not enter the brackets in commands.

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[  ]Square brackets indicate an optional item; if the brackets surround 
several words, all must be entered as a group. The brackets are not 
entered.
¼An ellipsis follows an item that may appear more than once. The 
ellipsis itself does not appear in commands.
|The vertical bar indicates a choice between items on either side of 
it. Do not include the bar in the command.
UPPERcaseUppercase letters in the command syntax are required; lowercase 
letters may be omitted. 

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Because Verilog identifiers are case sensitive, identifiers in 
simulation commands are case sensitive by default. VHDL 
identifiers are considered to be lower case. For example, to use the 
simulation command examine on the value of a Verilog register 
named MyRegister, you would type the following: 
examine MyRegister
To avoid case-mismatching problems, the TCL variable 
ObjectsCaseSensitivite and the corresponding entry in the 
quickhdl.ini file are ignored. For more information, see ªCase 
Sensitivity Requirements in VHDL/Verilog Instantiationsº on 
page 4-8
monospaced Monospaced type is used in examples.
--  #Comments are preceded by the number sign (#) or by two 
hyphens (--).
Numbers in non-decimal radixes are expressed using the form:
-radix#value
where:
±Indicates a negative number.

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radixCan be any base in the range 2 through 16. By default, numbers 
are assumed to be decimal.
#Is a required delimiter between the radix and the value.
valueSpecifies the numeric value, expressed in the specified radix.

Signal Pathnames
Signals are organized hierarchically. Each package, block statement, and 
component instantiation statement creates a new level in the hierarchy.
Signal names can be absolute or relative. Absolute names are preceded by a slash 
(/), which signifies the top level. Relative pathnames are relative to the current 
signal environment. The special names referring to the current signal environment 
(.) and the parent environment (..) can also be used. 

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By default, the slash (/) is used as the separator in hierarchical 
names. If you want to use a period (.) instead, you can set the 
VerilogNaming variable to 1, as follows:
set VerilogNaming 1
For more information on signal environments, see the environment command on 
page 8-38.
Array signals can be sliced or indexed. Indexes must be numeric, since the 
simulator does not know the actual index types.
Fields in record signals can be specified using the form:
signal_name.field_name

Examples
clkSpecifies the signal clk in the current environment. 
/clkSpecifies the signal clk in the top-level design unit. (These are 
equivalent if the environment is /.)

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/block1/u2/clkSpecifies the signal clk, two levels down from the top-level 
design unit.
block1/u2/clkSpecifies the signal clk, two levels down from the current 
environment. (This and the previous example are equivalent if the 
environment is /.)
array_sig(4)Specifies an index of an array signal.
array_sig(1 to 10)
Specifies a slice of an array signal.
record_sig.field 
Specifies a field of a record.

Wildcard Characters
Wildcard characters can be used in signal names in some simulator commands. 
Conventions for wildcards are as follows:
*Matches any sequence of characters.
?Matches any single character.
You can use square brackets [ ] in wildcard specifications if you place the entire 
name in curly braces { }:
{[abcd]}Matches any character in the specified set.
{[a±d]}Matches any character in the specified range.
{[^a±d]}Matches any character not in the set.

Examples
*Matches all signals.
{*[0-9]}Matches all signals ending in a digit.

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{?in*[0-9]}Matches such signal names as pin1, fin9, and binary2.

Values of VHDL Objects
Values of VHDL objects, such as variables and signals, can be referenced in 
simulator commands by preceding the name of the VHDL object with the 
percent % character. For example:
...
if {%counter = 23} ...
...
Values of VHDL variables can only be accessed after a step command or at a 
breakpoint in the VHDL region in which they exist.
If you want to prevent the percent sign from being interpreted as a VHDL object, 
double the percent sign. For example, %%counter will not be interpreted as a 
VHDL object.
If you need more flexibility in specifying the radix of the VHDL variable, use Tcl 
command substitution. For example:
...
if { [examine -bin counter] = ª01101110 } ...

Variables
Variables can be referenced in simulator commands by preceding the name of the 
variable with the dollar sign ($) character. The simulator looks first for the 
simulator state variables, then UNIX environment variables, then simulator 
control variables and user-defined variables.

Simulator State Variables
The available simulator variables are listed below. Note that case is not important.
$nRepresents a macro parameter, where n can be an integer in the 
range 1-9.

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argcReturns the total number of macro parameters passed.
$architectureReturns the name of the top-level architecture currently being 
simulated. For a configuration, this variable returns an empty 
string.
$deltaReturns the number of the current simulator iteration.
$entityReturns the name of the top-level entity currently being 
simulated. 
$envReturns the pathname of the current signal environment.
$nowReturns the current simulation time, which is a number expressed 
in the current simulation time resolution. 
$resolutionReturns the current simulation time resolution. 
For example:
echo ªThe time is $now $resolution.º
The example will result in:
The time is 12390 microseconds.
If you want to prevent the dollar sign as denoting a simulator variable, repeat the 
dollar sign. For example, $$now will not be interpreted as the current simulator 
time. 

Verilog Literals 
Verilog style literals are allowed in a QHSIM command. You may use either 
Verilog or VHDL style literals independent of the type of object operated on. For 
example, the following command may modify either a Verilog or VHDL variable:
change var ©hff 

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Simulator Control Variables
When you are running qhsim in the Tcl mode, there are a number of predefined 
Tcl variables that control aspects of the simulator that were previously only 
accessible via the quickhdl.ini file or a dialog box in the graphical interface. These 
control variables are shown in Table 8-1. 
Table 8-1. Simulator Control Variables 
Variable Name
Value Range
Purpose
BreakOnAssertion
0-4
Defines severity of assertion that causes a 
simulation break (0 = note, 2 = error, 
3 = failure, 4 = fatal)
CheckpointCompress
Mode
0,1
If 1, checkpoint/restore files are compressed
DefaultForceKind
freeze, drive, 
or deposit
If 1, checkpoint/restore files are compressed
DefaultRadix
0, 2, 8, 10, 16
same as Default Radix field of Main>Props 
simulation category popup menu.
DelayFileOpen
0, 1
same as DefaultFileOpen field of quickhdl.ini 
file
EnableXdefaultsWrite
0, 1
if 1, enables writing of the $HOME/.Xdefaults 
file when qhsim colors are changed.
IgnoreNote
0,1
If 1, ignore assertion notes
IgnoreWarning
0,1
If 1, ignore assertion warnings
IgnoreError
0,1
If 1, ignore assertion errors
IgnoreFailure
0,1
If 1, ignore assertion failures
InterpolateAnalog
0, 1
if 1, draws diagonal lines between successive 
analog values, otherwise draws rectilinear 
lines.
IterationLimit
positive
integer
Limit on simulation kernel iterations during 
one time delta

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Table 8-1. Simulator Control Variables  [continued]
ListCollapseDeltas
0, 1
same as the Deltas field of the 
List>Props>Defaults popup. A1 indicates 
that deltas will be collapsed.
ListDefaultsTrigger
0, 1
Same as the Trigger field of the 
List>Props>Defaults popup. A 1 indicates 
that signals will trigger the list display.
List 
DefaultShortName
0, 1
Same as the Trigger field of the 
List>Props>Defaults popup. A 1 
corresponds to Short Name and to Full 
Name.
ListStrobePeriod
positive 
integer
same as the Strobe Period field of the 
List>Props>Triggers popup menu.
ListStrobeStart
positive 
integer
same as the ªFirst strobe atº field of the 
List>Props>Triggers popup menu.
ListUseSignalTriggers
0, 1
same as the Signals button of the Trigger on 
field of the List>Props>Triggers popup. A 1 
indicates that signal triggering is active.
ListUseStrobe
0, 1
same as the Signals button of the Trigger on 
field of the List>Props>Triggers popup. A 1 
indicates that strobe is active.
NumericStdNo
Warnings
0, 1
if a 1, warnings generated within the 
accelerated numeric_std and numeric_bit 
packages are suppressed
ObjectsCaseSensitive
0,1
NOTE: This variable and the corresponding 
quickhdl.ini entry are currently ignored by 
QuickHDL.
RunLength
positive
integer
Default simulation length, in units of 
simulation resolution
SignalViewMask
0-15
determines what kinds of signals are 
displayed. the value is a sum of the following:
view input 1
view outputs 2
view inouts 4
view internals 8

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Table 8-1. Simulator Control Variables  [continued]
StdArithNoWarnings
0, 1
if a 1, warnings generated within the 
accelerated Synopsys packages suppressed
SupressTclResult
0,1
If 1, all qhsim command -quiet switches are 
activated and all Tcl command results are 
suppressed from the screen display
TclEscapeString
string
Characters that are allowed to follow a 
backslash and be interpreted as a Tcl escape 
sequence (if UseTclEscapes is ªonº)
UseTclEscapes
on, off
If ªoffº, all printable characters except the 
backslash (\) and double quote (ª) are allowed 
to follow the \ at the beginning of an extended 
identifier appearing in Tcl command;
If ªonº, those defined in the TclEscapeString 
are interpreted as Tcl escape sequences
VerilogNaming
0, 1
if a 1, hierarchical paths are entered on the 
command line and printed in Verilog notation. 
Extended identifiers my be entered using 
Verilog notation.
WaveSignalName
Width
positive 
integer
same as the Max Signal Name Width field of 
the Wave>Props>Display popup menu.
Because Verilog identifiers are case sensitive, identifiers in qhsim commands are 
now case sensitive by default. VHDL identifiers are considered to be lower case. 
For example, to examine the value of a Verilog register named MyRegister, you 
would type the following qhsim command: 
examine MyRegister
Note that the commands tcl_escapes and set_tcl_escapes have the same effect as 
the last two variables in the preceding table.

User-Defined Variables
User-defined variables are available with the set command. Like simulator 
variables, user-defined variables are preceded by a dollar sign when referenced. 
Create a variable with the set command:

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set var user1
Use the variable in a command like:
echo ªuser1 = $user1º
In prior releases, the backslash (\) was used to prevent the dollar sign ($) and per 
cent character (%) from being interpreted as references to simulator variables or to 
VHDL objects. In VHDL 93, the backslash is used to delimit extended identifiers, 
so to escape the dollar sign or per cent sign, use two of the characters, as in this 
example:
ECHO ª$$now = $nowº
FORCE string_signal ªstring with %% embeddedº

Simulation Time Units
You can specify the time unit for delays in all the simulator commands:
force clk 1 50 ns, 1 100 ns -repeat 1 us
run 2 ms
Note that all the time units in a simulator command need not be the same.
Unless you specify otherwise as in the examples above, simulation time is always 
expressed using the resolution units that are specified at the beginning of a 
simulation session in the Startup window.
By default, the specified time units are assumed to be relative to the current time 
unless the value is preceded by the character @, which signifies an absolute time 
specification. 

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abort
The abort command halts the execution of a macro file interrupted by a 
breakpoint.

Usage
ABOrt

See also
onbreak
resume
run

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bd
The bd command deletes a breakpoint.

Usage
BD <filename> <line>

Arguments
-<filename>
Specifies the name of the VHDL source file in which the breakpoint is to be 
deleted. The filename must match the one used to previously set the 
breakpoint, including whether a full pathname or a relative name was used.
-<line>
Specifies the line number of the breakpoint to be deleted.

Examples
bd alu.vhd 127
Deletes the breakpoint at line 127 in the source file named alu.vhd.

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bp
The bp (breakpoint) command sets a breakpoint. If the source file name and line 
number are omitted, this command lists all the breakpoints that are currently set. 
Otherwise, the command sets a breakpoint in the specified file at the specified 
line. Once set, the breakpoint affects every instance in the design.

Usage
BP [ <filename>  <line_number>  [ { <command> ¼ } ] ]

Arguments
-filename
Specifies the name of the VHDL source file in which the breakpoint is to be 
set; if omitted, all current breakpoints are listed.
-line_number
Specifies the line number at which the breakpoint is to be set; if omitted, all 
current breakpoints are listed.
-command
Specifies one or more QuickHDL commands that are to be executed at the 
breakpoint. Optional. Any text that follows the line number is treated as a 
command. Multiple commands must be separated by semicolons (;) unless Tcl 
is used, in which case commands may be placed on multiple lines. When Tcl is 
used, the entire command must be placed within curly braces, { }. 
You many include a continue command as the last command in the bp 
command string. It is an error to execute any commands within a bp command 
string following a continue, run, or step command. This applies if macros are 
used with the bp command string as well. A resume command should not be 
used.
If many commands are needed after the breakpoint, they can be placed in a 
macro file.

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Examples
bp
Lists all existing breakpoints, together with the source file names and any 
commands that have been assigned to breakpoints.
bp alu.vhd 147
Sets a breakpoint in the VHDL source file alu.vhd at line 147.
bp alu.vhd 147 {do macro.do}
Executes the macro.do macro file after the breakpoint.
bp test.vhd 22 {exa var1; exa var2}
Sets a breakpoint at line 22 of the file test.vhd and examines the values of 
variables var1 and var2. 
bp test.vhd 14 if $$now /= 100 cont; endif
bp test.vhd 14 {if {$now /= 100} then {cont} }
Non-Tcl and Tcl versions are shown above.
Sets a breakpoint in every instantiation of the file test.vhd at line 14. When that 
breakpoint is executed, the command is run. This command causes the simulator 
to continue if the current simulation time is not 100.

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Using two dollar signs ($$) prevents the $now variable from being 
evaluated until the breakpoint. Otherwise, it would be evaluated 
when the bp command is entered. In Tcl, two dollar signs are not 
needed because the curly braces postpone evaluation of everything 
they enclose. 

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change
The change command modifies the value of a variable. The simulator must be at a 
breakpoint or paused after a step command.

Usage
CHAnge <variable> <value>

Arguments
-variable
Specifies the name of a variable. The variable name must specify a scalar type 
or a one-dimensional array of character enumeration. You may also specify a 
record subelement, an indexed array, or a sliced array as long as the type is one 
of the above.
-value
Defines a value for the variable. The specified value must be appropriate for 
the type of the variable.

Examples
cha count 16#FFFF
Changes the value of the variable count to the hexadecimal value FFFF.

See also
force

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check contention add
The check contention add command enables contention checking for the 
specified nodes. The allowed nodes are Verilog nets and VHDL signals of 
std_logic and std_logic_vector. Any other node types and nodes that don©t have 
multiple drivers are silently ignored by the command.

Syntax
check contention add [ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ]
<node_name>...

Description of Contention Checking
Bus contention checking detects bus fights on nodes that have multiple drivers. A 
bus fight occurs when two or more drivers drive a node with the same strength and 
that strength is the strongest of all drivers currently driving the node. The 
following table provides some examples for two drivers driving a std_logic signal:
Table 8-2. Bus Contention Examples
driver 1
driver 2
fight
Z
Z
no 
0
0
yes 
1
Z
no 
0
1
yes 
L
1
no 
L
H
yes 
Detection of a bus fight results in an error message specifying the node and its 
drivers current driving values. If a node©s drivers later change value and the node 
is still in contention, a message is issued giving the new values of the drivers. A 
message is also issued when the contention ends. The bus contention checking 
commands can be used on VHDL and Verilog designs.

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Arguments
±rSpecifies that contention checking is enabled recursively into 
subregions. Optional; if omitted, contention check enabling is 
limited to the current region.
±inEnables checking on nodes of mode IN. Optional.
±outEnables checking on nodes of mode OUT. Optional.
±inoutEnables checking on nodes of mode INOUT. Optional.
±internalEnables checking on internal items. Optional.
±portsEnables checking on nodes of modes IN, OUT, or INOUT. 
Optional.
<node_name>
Enables checking for the named node.

See also
check contention config
check contention off
ªBus Contention Checkingº on page G-11

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check contention config
The check contention config command allow you to write checking messages to 
a file (default displays the message on your screen). You may also configure the 
contention time limit.

Syntax
check contention config [ ±file <filename> ] [ ±time <limit> ] 
[-command <cmd>

Description
See ªDescription of Contention Checkingº on page 8-16

Arguments
±file <filename> 
Specifies a file to write contention messages to. Optional. If this 
option is selected, the messages are not displayed to the screen.
±time <limit>
Specifies a time limit that a node may be in contention. Optional. 
Contention is detected if a node is in contention for as long as or 
longer than the limit. The default limit is 0.
-command <cmd>
switch allows the report to be generated by a custom TCL 
command that takes 6 arguments and gets called in the following 
sequence:
-init <filename> {} {} {} {} 
This call occurs once and the filename argument value is determined 
by the -file option (can be an empty string).
-violation <signalname> <start> <finish> <duration> <limit>
This call occurs for each violation. The signalname argument is the 
hierarchical name of the signal. The start argument is the time that 
the signal contention started. The finish argument is the time that the 
violation is reported. The duration is the difference between start 

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and finish. The limit argument is the constraint specified with the -
time option (0 if not specified). The times are strings that include the 
resolution (for example:  ª100 nsº).
-driver <drivername> <drivervalue> {} {} {}
Each violation is followed by two or more of these calls. The 
drivername argument is the hierarchical name of the driving process 
or driving output port. The drivervalue argument is the value of the 
driver.
-end {} {} {} {} {}
This call terminates the list of drivers.
-done {} {} {} {} {}
This call occurs at the end of the simulation.

Contention Message Reporting
There is no explicit command to view the message file. The default error message 
format look like the following:
 ** Error: Contention violation on /test/sig(1).
          Now: 130 ns  Start: 120 ns  Duration: 10 ns  
Constraint: 5 ns
                     /test/a/n01 = 0
                     /test/b/n01 = 1
        ** Error: Contention violation on /test/sig(1).
          Now: 140 ns  Start: 130 ns  Duration: 10 ns  
Constraint: 5 ns
                     /test/a/n01 = 0
                     /test/b/n01 = 1
                     /test/c/n02 = 1
where /test/a is the instance and n01 is the pin, etc. If the contention time was less 
than 5 ns, then no error would occur in this example. You can customize the report 
format through the -command usage model.

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Checkpoint/Reset. When the designer checkpoints a design, the message file is 
closed. When a designer resets the simulator the contention checking mode and 
configuration are retained.

See also
ªBus Contention Checkingº on page G-11

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check contention off 
The check contention off command disables contention checking for the 
specified nodes. 

Syntax
check contention off 
[ ±all ] [ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ] <node_name>...

Description
See ªDescription of Contention Checkingº on page 8-16

Arguments
±allDisables contention checking for all nodes that have checking 
enabled. Optional.
±rSpecifies that contention checking is disabled recursively into 
subregions. Optional; if omitted, contention check disabling is 
limited to the current region.
±inDisables checking on nodes of mode IN. Optional.
±outDisables checking on nodes of mode OUT. Optional.
±inoutDisables checking on nodes of mode INOUT. Optional.
±internalDisables checking on internal items. Optional.
±portsDisables checking on nodes of modes IN, OUT, or INOUT. 
Optional.
<node_name>Disables checking for the named node. 

See also
check contention add
check contention config
ªBus Contention Checkingº on page G-11

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check float add 
The check float add command enables float checking for the specified nodes. The 
allowed nodes are Verilog nets and VHDL signals of type std_logic and 
std_logic_vector (other types are silently ignored).

Syntax
check float add 
[ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ] <node_name>...

Description of Float Checking
Bus float checking detects nodes that are in the high impedance state for a time 
equal to or exceeding a user-defined limit. This is an error in some technologies. 
Detection of a float violation results in an error message identifying the node. A 
message is also issued when the float violation ends. The bus float checking 
commands can be used on VHDL and Verilog designs.

Arguments
±rSpecifies that float checking is enabled recursively into 
subregions. Optional; if omitted, float check enabling is limited to 
the current region.
±inEnables checking on nodes of mode IN. Optional.
±outEnables checking on nodes of mode OUT. Optional.
±inoutEnables checking on nodes of mode INOUT. Optional.
±internalEnables checking on internal items. Optional.
±portsEnables checking on nodes of modes IN, OUT, or INOUT. 
Optional.
<node_name>
Enables checking for the named node.

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See also
ªBus Float Checkingº on page G-12

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check float config
The check float config command allow you to write checking messages to a file 
(default displays the message on your screen). You may also configure the float 
time limit.

Syntax
check float config [ ±file <filename> ] [ ±time <limit> ]

Description
See ªDescription of Float Checkingº on page 8-22

Arguments
±file <filename>
Specifies a file to write float messages to. Optional. If this option 
is selected, the messages are not displayed to the screen.
±time <limit>
Specifies a time limit that a node may be floating. Optional. An 
error is detected if a node is floating for as long as or longer than 
the limit. The default limit is 0.

See also
ªBus Float Checkingº on page G-12

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check float off
The check float off command disables float checking for the specified nodes. 

Syntax
check float off [ ±all ] [ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ]
<node_name>...

Description
See ªDescription of Float Checkingº on page 8-22

Arguments
±allDisables float checking for all nodes that have checking enabled. 
Optional.
±rSpecifies that float checking is disabled recursively into 
subregions. Optional; if omitted, float check disabling is limited 
to the current region.
±inDisables checking on nodes of mode IN. Optional.
±outDisables checking on nodes of mode OUT. Optional.
±inoutDisables checking on nodes of mode INOUT. Optional.
±internalDisables checking on internal items. Optional.
±portsDisables checking on nodes of modes IN, OUT, or INOUT. 
Optional.
<node_name>
Disables checking for the named node.

See also
ªBus Float Checkingº on page G-12

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check stable on 
The check stable on command enables stability checking on the entire design. 
Design stability checking detects when circuit activity has not settled within a 
user-defined period for synchronous designs. 

Syntax
check stable on  [ ±file <filename> ] [ ±period <time> ] [ ±strobe <time> ]

Description of Stability Checking
Design stability checking detects when circuit activity has not settled within a 
user-defined period for synchronous designs. The user specifies the clock period 
(-period <time>) for the design and the strobe time within the period that the 
circuit must be stable at. A violation is detected and an error message is issued if 
there are pending driver events at the strobe time. The message identifies the 
driver that has a pending event, the node that it drives, and the cycle number. The 
design stability checking commands can be used on VHDL and Verilog designs.

Arguments
±file <filename>
Specifies a file to write the error messages to. If this option is 
selected, the messages are not displayed to the screen. Optional.
±period <time>
Specifies the clock period (which is assumed to begin at the time 
the check stable on command is issued). Optional. This option is 
required the first time you invoke the check stable on command. It 
is not required if you later enable checking after it was disabled 
with the <bookmark (cmd)>check stable off command. 
±strobe <time>
Specifies the elapsed time within each clock cycle that the 
stability check is performed. Optional. The default strobe time is 
the period time. If the strobe time falls on a period boundary, then 
the check is performed one timestep earlier. Normally the strobe 
time is specified as less than or equal to the period, but if it is 
greater than the period, then the check will skip cycles. 

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Reporting
There is no explicit command to view the message file. The default error message 
format looks like the following:
Error:  Delay over period violation on instance /top/a at 
<pattern> and time
        12000 ns.
  Unprocessed events:  Drive signal /top/a/b(0) to '1'
where pattern is the integer part of this equation: ([total_time/period] + 1).
Vendors can customize the report format through the -command usage model.
The period and strobe information specified by the designer is saved at the top of 
the message report (as a comment) for use by other tools.
Checkpoint/Reset. When the designer checkpoints a design, the message file is 
closed. When a designer resets the simulator the delay over period checking mode 
is retained.

Examples
check stable on -period "100 ps -strobe "199 ps" 
Results in a stability check 99 ps into each even numbered clock cycle (cycle 
numbers start at 1).

See also
ªDesign Stability Checkingº on page G-12

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check stable off
The check stable off command disables stability checking. You may later enable 
it with check stable on, and, meanwhile, the clock cycle numbers and boundaries 
are still kept track of. 

Syntax
check stable off

Description
See ªDescription of Stability Checkingº on page 8-26

Arguments
None.

See also
ªDesign Stability Checkingº on page G-12

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checkpoint 

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The checkpoint command is not available for Verilog for this 
release. It will be provided in a subsequent release. 
The checkpoint command saves the state of your simulation. The checkpoint 
command saves the simulation kernel state, the vsim.wav file, the list of signals 
shown in the List and Wave windows, the pointer positions for files opened under 
VHDL, and the states of foreign architectures, LMG SmartModels, and LMG 
Smart Modeler. Changes you made interactively while running qhsim are not 
saved; for example, qhsim macros, command-line interface additions like user-
defined commands, and states of graphical user interface windows are not saved. 
The checkpoint command can be used only if QuickHDL is not invoked with the 
-schematic option (see Chapter 5, ªAdditional Informationº for the qhsim 
command). 
Note that the checkpoint file is normally compressed. If you want to change this 
default, use the Tcl variable CheckpointCompressMode: 0 to turn off 
compression. Setting CheckpointCompressMode: 1 turns compression back on. 

Usage
CHEckpoint  <file_name>

Arguments
-filename
Specifies the name of the checkpoint file.

See also
restore
restart
ªHow to Use Checkpoint and Restore Commandsº on page G-1
ªUsing Macros with Restart and Checkpoint/Restoreº on page G-3

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continue
The continue command continues a simulation run after a step command, 
stepover command, or a breakpoint. A continue command may be input 
manually or used as the last command in a bp command string.

Usage
CONtinue

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describe
The describe command displays information about the type of a variable or signal 
in the Transcript window. To describe a variable, the simulator must be paused 
after a step command or at a breakpoint. A signal can be described at any time. 
The describe command returns its results as a Tcl string.

Usage
DEScribe <variable_name> [-Quiet]   

Arguments
-variable_name
Specifies the name of a signal or variable. Required. 

Options
--Quiet
Specifies that the command does not appear on the screen (no echo). Optional. 

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disablebp
The disablebp command temporarily turns off all existing breakpoints. To turn 
the breakpoints back on again, use the enablebp command.

Usage
DISablebp

See also
enablebp
onbreak
resume

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do
The do command executes commands contained in a macro file. A macro file can 
have any name and extension. An error in a macro file causes its execution to be 
interrupted.

Usage
DO <filename>  [ <parameter_value> ¼]

Arguments
-<filename>
Specifies the name of the macro file to be executed. The name can be a 
pathname or a relative file name. 
Relative pathnames are relative to the current working directory if the do 
command is executed from the command line. If the do command is executed 
from another macro file, relative pathnames are relative to the directory of the 
calling macro file. This allows groups of macro files to be moved to another 
directory and still work.
-<parameter_value>
Specifies up to nine values that are to be passed to the corresponding 
parameters $1 through $9 in the macro file. Multiple parameter values must be 
separated by spaces. If you specify fewer parameter values than the number of 
parameters used in the macro, the unspecified values are treated as empty 
strings in the macro.
Note that there is no limit to the number of parameters that can be passed to 
macros, but only nine values are visible at one time. You can use the shift 
command to see the other parameters. The argc variable returns the number of 
parameters that are passed.

Examples
do macros/stimulus 100
This command executes the file macros/stimulus, passing the parameter value 100 
to $1 in the macro file.

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do testfile design.vhd 127
If the macro file testfile contains the line bp $1 $2, this command would place a 
breakpoint in the VHDL source file named design.vhd at line 127.

Description
If you are executing a macro (DO file) when your simulation hits a breakpoint 
or causes a run-time error, the simulator interrupts the macro and returns 
control to the command line.
To continue as if the breakpoint had not been executed, use the continue 
command to complete the run command that was interrupted. Then use the 
resume command to continue running the macro.
Also note that the onbreak command allows you to specify a command to run 
when you hit a breakpoint within a macro.

See also
onbreak
resume
shift
Variables
ªPassing Parameters to Macrosº on page G-5

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drivers
The drivers command displays in the Transcript window the current value and 
scheduled future values for all the drivers of a specified signal. If the signal is a 
record or array, only the drivers for the first subelement are shown. This command 
reveals the operation of transport and inertial delays and assists in debugging 
models. 
The drivers command returns its results as a Tcl string.

Usage
DRIvers <signal_name>... [-Quiet]

Arguments
-<signal_name>
Specifies the name of the signal whose values are to be output. All signal types 
are valid. Required. 

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

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echo
The echo command displays a specified message in the Transcript window.

Usage
ECHO <text_string>

Argument
-<text_string>
Specifies the message text to be displayed. If the text string is surrounded by 
quotes, blank spaces are displayed as entered. If quotes are omitted, two or 
more adjacent blank spaces are compressed into one space.

Examples
ECHO ªThe time is   $now ns.º
If the current time is 1000 ns, this command produces the message:
The time is   1000 ns.
If the quotes are omitted, all blank spaces of two or more are compressed into one 
space.
ECHO The value of counter is %counter.
If the current value of counter is 21, this command produces the message:
The value of counter is 21.
Echo can also use command substitution, such as:
ECHO The hex value of counter is [examine -hex counter].
If the current value of counter is 21 (hex 15), this command produces:
The value of counter is 15.

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enablebp
The enablebp command turns on all breakpoints turned off by the disablebp 
command.

Usage
ENablebp

See also
disablebp
onbreak
resume

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environment
The environment command lets you display or change the current signal 
environment. 

Usage
ENVironment [<pathname>] [-Quiet]

Arguments
-<pathname>
Specifies the pathname to which the current signal environment is to be 
changed. Optional; if omitted, the command causes the pathname of the 
current signal environment to be displayed. Multiple levels of a pathname must 
be separated by slashes (/). Enter a single slash to indicate the top level. Enter 
two dots (..) to move up one level. 

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

Examples
env
Displays the pathname of the current signal environment.
env ..
Moves up one level in the design hierarchy.
env blk1/u2
Moves down two levels in the design hierarchy.
env /
Moves to the top level of the design hierarchy.

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examine
The examine command examines a variable or signal and displays its current 
value in the Transcript window. To examine a variable, the simulator must be 
paused after a step command or at a breakpoint. Signals can be examined at any 
time. The examine command also returns its results as a Tcl list (a list of strings 
separated by blanks).

Usage
EXAmine   -<radix>  <name> [-Quiet]  

Arguments
-±<radix>
Specifies the radix for the signals that follow in the command. Valid entries:
BINary
OCTal
DECimal (default for integers)
HEX
-<name>
Specifies the name of any variable or signal. All signal and variable types are 
allowed, except those of the type file. Required. 

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

Example
When Tcl is enabled, commands like find and examine return their results as a 
Tcl list (a blank-separated list of strings) so you can do things like:
foreach {find ABC*} {
...}
if {[examine -bin signal_12] == ª1110111XXXZº} {...
examine -hex [find *]}

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find
The find command displays the full pathnames of all signals whose names match 
the signal name specification you provide. If no signal mode is specified, all 
interface signals and internal signals are found (that is, all signals of modes IN, 
OUT, INOUT, and INTERNAL).
The find command returns its results as a Tcl list (a list of strings separated by 
blanks).

Usage
-FIND [Recursive ] [ ±IN ] [ ±OUT ] [ ±INOut ] [ ±INTernal ]
[ ±Ports ] [-Quiet] <signal_name> 

Options
-±Recursive
Specifies that the scope of the search is to descend recursively into subregions; 
if omitted, the search is limited to the selected region.
-±IN
Specifies that the scope of the search is to include signals of mode IN.
-±OUT
Specifies that the scope of the search is to include signals of mode OUT.
-±INOut
Specifies that the scope of the search is to include signals of mode INOUT.
-±INTernal
Specifies that the scope of the search is to include internal signals.
-±Ports
Specifies that the scope of the search is to include signals of modes IN, OUT, 
or INOUT.
--Quiet
Keeps the output from appearing on the screen.

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Arguments
-<signal_name>
Specifies the signal name for which you want to search. Wildcard characters 
are allowed.

Examples
find -r /*
Finds all signals in the entire design.
find *
Displays the names of all signals in the current region.

See also
Wildcard Characters

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force
The force command allows you to apply stimulus to signals interactively. Since 
force commands can be included in a macro file, it is possible to create complex 
sequences of stimuli. 

Usage
FORCE [ -Freeze | -DRive | -DEposit] [-Repeat <period>] <signal_name> 
<value> [ <time> ] [ , <value> <time> ¼]

Options
--Freeze
Freezes the signal at the specified value until it is forced again or until it is 
unforced with a noforce command.
--DRive
Attaches a driver to the signal and drives the specified value until the signal is 
forced again or until it is unforced with a noforce command. This option is 
illegal for unresolved signals.
--DEposit
Sets the signal to the specified value. The value remains until there is a 
subsequent driver transaction, or until the signal is forced again, or until it is 
unforced with a noforce command. 
If you do not use one of the -freeze, -drive, or -deposit options, then -freeze is 
the default for unresolved signals and -drive is the default for resolved signals. 

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If you prefer -freeze as the default for both resolved and unresolved signals, 
you can change the default force kind in the quickhdl.ini file; see Chapter 9.

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The QuickHDL v8.5_4.6b release contains a change in the way 
ªdepositº forces (which correspond to QuickSim II ªchargeº forces) 
are applied. Prior to this release, deposit forces were applied at the end 
of the specified time, thus overriding scheduled signal changes 
occurring at any delta during that time. Starting with this release, 
deposit forces are applied immediately, at delta zero of the specified 
time. Because of this, such forces may be overridden by signal 
changes that occur in subsequent deltas within that time. This new 
force behavior is more consistent with that exhibited by QuickSim II.
Consider an EV design having a boundary net ªbndry_netº connected 
to a pull-up resistor on the QuickSim II side of the boundary and a 
VHDL component on the QuickHDL side. Since QuickHDL owns the 
boundary net, it resolves its signal value. Assume that the net is given 
a charge forced at time 0 with value `0'. As the excerpt from the 
QuickHDL list window below shows, the force is seen at time 0 delta 
+0. At delta +1, an `H' value arrives at the net from QuickSim II, 
having propagated through the pull-up resistor, and overrides the 
force.
In previous releases, the net had value `U' at time 0 +0, and the force 
value `0' was seen at time 0 +1.
The behaviors of the QuickHDL ªfreezeº and ªdriveº force types 
have not changed. These correspond to and behave consistently with 
QuickSim II ªfixedº and ªwiredº force types, respectively. 
-±Repeat <period>
Repeats the force command, where period is the amount of time of the repeat 
period.

Arguments
-<signal_name>
Specifies the name of the signal to be forced. A wildcard is permitted only if it 
matches one signal. See ªSignal pathnamesº at the beginning of this chapter 
for the full syntax of a signal name. The signal name must specify a scalar type 

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or a one-dimensional array of character enumeration. You may also specify a 
record subelement, an indexed array, or a sliced array, as long as the type is 
one of the above.
-<value>
Specifies the value that the signal is forced to. The specified value must be 
appropriate for the signal type.
A one-dimensional array of character enumeration can be forced as a sequence 
of character literals or as a based number with a radix of 2, 8, 10 or 16. For 
example, the following values are equivalent for a signal of type bit_vector (0 
to 3):
1111
-- character literal sequence
2#1111
-- binary radix
10#15
-- decimal radix
16#F
-- hexadecimal radix
For based numbers, the simulator converts each 1 or 0 in the value to one of the 
values in the enumerated type. This translation is specified by the Force1 and 
Force0 lines in the quickhdl.ini file. If the simulator cannot find a translation 
for 0 or 1, it uses the left bound of the signal type (type'left) for that value.
-<time>
Specifies the time that the value is applied. The time is relative to the current 
time unless an absolute time is specified by preceding the value with the 
character @. If the time units are not specified, then the default is the 
resolution units selected at simulation start-up. A zero-delay force command 
causes the change to occur in the current (rather than the next) delta. Optional. 

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Examples
force input1 0
Forces the signal input1 to 0 at the current simulator time. 
force bus1 01XZ 100 ns
Forces the signal bus1 to 01XZ at 100 nanoseconds after the current simulator 
time.
force bus1 16#f @200
Forces the signal bus1 to 16#F at the absolute time 200 measured in the resolution 
units selected at simulation start-up.
force input1 1 10, 0 20 -r 100
Forces the signal input1 to 1 at 10 time units after the current simulator time and 
to 0 at 20 time units after the current simulation time. This repeats every 100 time 

See also
noforce

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format list
The format list command records the names of the signals currently being listed 
and the list options for each signal as a file of list commands. This file may be 
invoked with the do command to recreate the LIST window format on a 
subsequent simulation run.

Usage
FORMAT LIST <filename>

Arguments
-LIST
Specifies that the contents of the List window are to be recorded.
-<filename>
Specifies the name of the output file where the data is to be written.

Examples
format list alu_list.do
Saves the current data in the List window in a file named alu_list.do.

See also
do
list

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format wave
The format wave command records the names of the signals currently being 
displayed in the Wave window and the display options for each signal as a file of 
wave commands. This file may be invoked with the do command to recreate the 
wave window format on a subsequent simulation run.

Usage
FORMAT WAVE <filename>

Arguments
-WAVE
Specifies that the contents of the Wave window are to be recorded.
-<filename>
Specifies the name of the output file where the data is to be written.

Examples
format wave alu_wave.do
Saves the current data in the Wave window in a file named alu_wave.do.

See also
do
wave

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if
The if command executes other commands if the specified expression is true. If 
the command is placed in a macro file, the keywords if, else, and endif must be the 
first tokens on a line. If used in interactive mode or from a breakpoint command, 
the entire command must be entered on the same line.
Note that if Tcl commands are enabled Ð and this is the default Ð then the Tcl if 
command described in appendix F is used, not this one.

Usage
IF expression
commands
[ ELSE
 commands ]
ENDIF

Arguments
-expression
Specifies a comparison operation that executes the subsequent command(s) if 
the comparison is true. If the comparison is false, the commands contained in 
any existing else clause are executed. The valid operators are relational:
= equal
/= not equal to
> greater than
< less than
>= greater than or equal
<= less than or equal
Operands may be VHDL objects or simulator variables.
VHDL objects may be signals, variables, or constants referenced by using a 
percent sign as described in the beginning of this section.
Simulator variables are preceded by a dollar sign as described in the beginning 
of this section.
If both operands are numeric, a numeric comparison is done using a decimal 
radix by default. (Other radixes can be specified.) If both operands are not 
numeric, a string comparison is done.

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-commands
Can be any simulator command. Multiple commands can appear on separate 
lines or on the same line. Commands on the same line must be separated by a 
semicolon (;).

Examples
if %counter = 23
 echo ªcounter = 23º ; echo ªcounter2 = 24º
else
  echo ªcounter /= 23º
  echo ªcounter2 /= 24º
endif
In this example, the VHDL variable named counter is tested for the value 23. If 
the condition is true, the message 
counter = 23
counter2 = 24
is displayed in the Transcript window. If the condition is false, then:
counter /= 23
counter2 /= 24
is displayed.

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list
The list
mode is specified, all interface signals and internal signals are listed. Without 
arguments, this command displays the List window. 

Usage
LIST [ ±Strobe [ <first_strobe>, ] <period> ] [ ±Collapse ] [ ±DELta | ±Nodality ]
[ [ ±Recursive ]     [ ±IN ] [ ±OUT ] [ ±INOut ]     [ ±INTernal ] [ ±Ports ]
[ ±<radix> ]     [ ±NOTrigger [ ±Trigger ] ]     ±Width <n>    
 <signal_name> [ = <new_name> ] ¼ ]

Options
-±Strobe [<first_strobe>,] <period>
Causes the list to be updated at a frequency specified by period beginning with 
the optional first_strobe. If all the signals are listed using the notrigger option, 
the list is only updated at the strobe times. To cancel a strobe directive, specify 
0 time units.
-±Collapse
A toggle controlling whether or not intermediate values or just final values are 
shown for each simulation time. 
-±DELta
Causes the number of simulator iterations to be included in the listing.
-±NODelta
Causes the number of iterations not to be included in the listing. A zero-delay 
signal assignment produces multiple simulator cycles without advancing the 
time. Each simulator cycle is an iteration.
-±Recursive
For use with wild card searches. Specifies that the scope of the search is to 
descend recursively into subregions; if omitted, the search is limited to the 
selected region.
-±IN
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode IN if they match the signal_name specification.

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-±OUT
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode OUT if they match the signal_name specification.
-±INOut
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode INOUT if they match the signal_name specification.
-±INTernal
For use with wild card searches. Specifies that the scope of the search is to 
include internal signals if they match the signal_name specification.
-±Ports
For use with wild card searches. Specifies that the scope of the listing is to 
include signals of modes IN, OUT, or INOUT.
-±<radix>
Specifies the radix for the signals that follow in the command. Valid entries 
are:
BINary
OCTal
DECimal (default for integers)
HEX
If no radix is specified for an enumerated type, a SYMBOLIC representation is 
used by default. In this representation, the actual values of the enumerated type 
of the specified signal(s) are listed. 
If you specify a radix for an array of an enumerated type, the simulator 
converts each signal value to 1, 0, Z, or X. This translation is specified by the 
List1, List0, and ListZ lines in the quickhdl.ini file. 
For example, the value R1 would be mapped to 1 in the List1 line in the 
quickhdl.ini file, as follows:
 List1 `1' TRUE R1
Any value that is not included in List1, List0, or ListZ is reported as an 
unknown (X).

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-±Trigger 
Specifies that signals that follow the flag are to be listed, and causes the List 
window to be updated when the signal changes. This option is the default, so it 
is needed only if notrigger is specified in the same list command. 
-±Notrigger
Specifies that signals following the flag are to be listed, but does not cause the 
List window to be updated when the signal changes. Optional. 
-±Width <n>
Specifies column width. Optional. 
-signal_name
Specifies the name of a signal to be listed. Wildcard characters are allowed. 
Optional. 

Arguments
-<new_name>
Specifies an alternative name to be displayed as a column heading in the list. 
This alternative name is not valid in a force or examine command, however.

Examples
list -r /*
Lists all signals in the design.
list *
Lists all signals in the region.
list -in *
Lists all input signals in the region.
list a /top/lower/sig = sig array_sig(9 to 23)
Displays a List window containing three columns headed a, sig, and array_sig(9 to 
23). 

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list clk -not a b c d
Lists clk, a, b, c, and d only when clk changes.
list -s 100
The list is updated every 100 time units
list -not clk a b c d
Lists clk, a, b, c, and d every 100 time units.
list -del
Includes the iteration number in the listing. 
list vec1 -hex vec2 -dec vec3 vec4
Lists the signal vec1 using symbolic values, lists vec2 in hexadecimal, and lists 
vec3 and vec4 in decimal.

See also
log

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log
The log command creates a log file containing simulation data for all signals 
whose names match the provided specifications. Signals that are displayed using 
the list and wave command are automatically recorded in the log file. The qhsim 
command creates a default log file named ªvsim.wavº.
If no signal mode is specified, the log file contains data for all signals in the 
selected region whose names match the signal name specification.
The log file is the source of data for the List and Wave output windows. A signal 
which has been logged and is subsequently added to the List or Wave window will 
have its complete history back to the start of logging available for listing.
The qhsim -view command is used to view the log file contents.

Usage
LOG [ ±Recursive ] [ ±IN ] [ ±OUT ] [ ±INOut ] [ ±Ports ] [ ±INTernal ]
<signal_name> ¼

Options
-
Specifies that the scope of the search is to descend recursively into subregions; 
if omitted, the search is limited to the selected region.
-±IN
Specifies that the log file is to include data for signals of mode IN whose 
names match the specification.
-±OUT
Specifies that the log file is to include data for signals of mode OUT whose 
names match the specification.
-±INOut
Specifies that the log file is to include data for signals of mode INOUT whose 
names match the specification.

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-±Ports
Specifies that the scope of the search is to include signals of modes IN, OUT, 
or INOUT.
-±INTernal
Specifies that the log file is to include data for internal signals whose names 
match the specification.

Arguments
-<signal_name>
Specifies the signal name which you want to log. Multiple signal names may 
be specified. Wildcard characters are allowed.

Examples
log -r /*
Logs all signals in the design. 
log -out *
Logs all output ports in the current design unit.

See also
list
qhsim -wave
qhsim -view
Wildcard Characters

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noforce
The noforce command removes the effect of any active force commands on the 
selected signals. This command also causes the signals effective value to be 
reevaluated and the signal to become active.

Usage
NOForce <signal_name> ¼

Arguments
-<signal_name>
Specifies the name of a signal. Must match the signal name used in the force 
command. Multiple signal names may be specified. Wildcard characters are 
allowed.

See also
force
Wildcard Characters

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nolist
The nolist command removes signals from the list window.

Usage
NOList <signal_name> ¼

Arguments
-<signal_name>
Specifies the name of a signal. Must match the signal name used in the list 
command. Multiple signal names may be specified. Wildcard characters are 
allowed.

See also
list
Wildcard Characters

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nowave
The nowave command removes signals from the Wave window.

Usage
NOWAVE <signal_name> ¼

Arguments
-<signal_name>
Specifies the name of a signal. Must match the signal name used in the wave 
command. Multiple signal names may be specified. Wildcard characters are 
allowed.

See also
wave
Wildcard Characters

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nowhen
The nowhen command deactivates selected when commands.

Usage
NOWHen    [ <label>]

Arguments
-<label>
Used to identify individual when commands. If omitted, the command 
performs no operation. To deactivate all when commands, use an asterisk (*) 
as the label.

Examples
99: when b {echo ªb changedº}
¼
nowhen 99
The nowhen command deactivates the when command labeled 99.
nowhen *
The nowhen command above deactivates all when commands.

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onbreak
The onbreak command is used only within a macro to specify a command to be 
executed when an active macro encounters a breakpoint in the VHDL source. Use 
the onbreak command without arguments to specify that no command is to be 
automatically executed when a macro encounters a breakpoint in the source code. 
In that case, the macro will be interrupted after a breakpoint occurs and after any 
associated bp command string is executed.
When Tcl commands are enabled, onbreak commands can contain macro calls.

Usage
ONBreak { [ <command> [ ; <command> ] ¼ ] }

Arguments
-<command>
Any simulator command can be used as an argument to onbreak. If you want 
to use more than one command, use a semicolon to separate the commands, 
unless Tcl is used, in which case commands may be placed on multiple lines. 
Using Tcl, the entire command string must be placed in curly braces. It is an 
error to execute any commands within an onbreak command string following 
a continue, step, or run command. This also applies if macros are used within 
the onbreak command string. Optional. 

Examples
onbreak {exa data ; cont}
Examine the value of the signal data when a breakpoint is encountered. Then 
continue the run command. 
onb {resume}
Resume execution of the macro file on encountering a breakpoint. 

See also
do
resume

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onerror
The onerror command is used only within a macro to specify a command to be 
executed when an active macro encounters an error. Use the onerror command 
without arguments to specify that no command is to be automatically executed 
when a macro encounters an error. Use onerror with a resume command to allow 
an error message to be printed without halting the execution of the macro file.

Usage
ONError { [ <command> [ ; <command> ] ¼ ] }

Arguments
-<command>
Any simulator command can be used as an argument to onerror. If you want 
to use more than one command, use a semicolon to separate the commands, 
unless Tcl is used, in which case commands may be placed on multiple lines. 
Using Tcl, the entire command string must be placed in curly braces. Optional. 

See also
onbreak

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pause
The pause command placed within a macro interrupts the execution of that macro. 

Usage
PAUSE
When the macro is interrupted, the simulator prompt changes to:
QHSIM (pause)23>
This ªpauseº prompt reminds you that a macro has been interrupted.
When a macro is paused, you may invoke another macro. If that macro gets 
interrupted, you can invoke another one, and so on Ð up to a nesting level of 50.
If this gets confusing, use the status command. It will show you which macros are 
interrupted, at what line number, and show you the interrupted command.

See also
continue
resume
status

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quit
The quit command exits the simulator without saving data.

Usage
QUIT [ ±Force ]

Options
-±Force
Quits without asking for confirmation; if omitted, the simulator asks you for 
confirmation before exiting.

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radix
The radix command specifies the default radix to be used. The command can be 
used at any time. The specific radix is used for all commands (force, examine, 
change, etc.) as well as for displayed values in the Signals, Variables, Dataflow, 
List, and Wave windows.

Usage
RADix [ Symbolic | Binary | Octal | Decimal | Hex ]

Options
If no options are used, the command returns the current default radix.

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restart
The restart command reloads the design and resets the simulation time to zero. , 
This command only reloads design elements that have changed.

Usage
REStart [ ±Force ] [ ±NOBreakpoint ] [ ±NOLIst ] [ ±NOLOg ] [ ±NOWave ]

Options
-±Force
Specifies that the simulation will be restarted without requiring confirmation in 
a pop-up window. Optional. 
-±NOBreakpoint
Specifies that all breakpoints will be removed when the simulation is restarted. 
The default is for all breakpoints to be reinstalled after the simulation is 
restarted.
-±NOLIst
Specifies that the current List window environment will not be maintained 
after the simulation is restarted. The default is for all currently listed signals 
and their formats to be maintained.
-±NOLOg
Specifies that the current logging environment will not be maintained after the 
simulation is restarted. The default is for all currently logged signals to 
continue to be logged.
-±NOWave
Specifies that the current Wave window environment will not be maintained 
after the simulation is restarted. The default is for all signals displayed in the 
Wave window to remain in the window with the same format.

See also
checkpoint
restore
ªUsing Macros with Restart and Checkpoint/Restoreº on page G-3

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restore 

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The restore command is not available for Verilog for this release. 
It will be provided in a subsequent release. 
The restore command restores the state of a simulation that was saved with a 
checkpoint command during the current invocation of qhsim. To restore while 
running the simulator, use restore. To start the simulator and restore a previously 
saved checkpoint, use the -restore option with the qhsim command. The restore 
command can be used only if QuickHDL is not invoked with the -schematic 
option (see Chapter 5, ªAdditional Informationº for the qhsim command). 
The restore command restores the following: 
-Simulation kernel state; vsim.wav file
-Signals listed in the List and Wave windows
-File pointer positions for files opened under VHDL
-States of foreign architectures, LMG SmartModels, and LMG Smart 
Modeler. 
The restore command does not restore the following:
-qhsim macros
-Command-line interface input, such as user-defined commands
-Graphical user interface windows

Usage
RESTORE <filename> [ -Nocompress] 

Arguments
-<filename>
Specifies the name of the checkpoint file. Required. 

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Options
--Nocompress
Specifies that the checkpoint file was not compressed when saved. Optional. 

See also
checkpoint
restart
ªHow to Use Checkpoint and Restore Commandsº on page G-1
ªUsing Macros with Restart and Checkpoint/Restoreº on page G-3

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resume
The resume command is used to resume execution of a macro file after a 
breakpoint. It may be input manually or placed in an onbreak command string. 
(Placing a resume command in a bp command string does not have this effect.) 
You can also use the resume command in an onerror command string to print an 
error message without halting execution of the macro file. 

Usage
RESUme

See also
abort
onbreak
run

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run
The run command advances the simulation by the specified number of time steps.

Usage
RUN [ <time_units> | -All | Next ]

Arguments
-<time_units>
Specifies the units of simulation time to be run. Optional; if omitted, the 
simulator runs for the default number of time units specified in the quickhdl.ini 
file. The default time units specification can be changed during a session by 
the Prop command in the Transcript window. 

Options
--All
Causes the simulator to run until there are no events scheduled. Optional. 
--Next
Causes the simulator to run to the next event time. Optional. 

Example
run 1000
Advances the simulator 1000 time steps.
run 10 ms
Advances the simulator 1000 the appropriate number of time steps corresponding 
to 10 milliseconds.

Exceptions
Using the RUN command (run, cont, or step) in a when statement is not 
supported. You don't need to use a RUN command, instead you can modify 
when statement:

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when {/io=º1º and /i1=º1º} {
echo ªStarting over at 00!º
<insert force commands here>
if {$count <= 1000} {
echo ªStill Running!º
incr count +1
} else {
echo ªSimulation Complete!º;
stop
}
}
Then, instead of starting the simulation with ªrun 40º use ªrun -allº and the 
simulation will continue until the conditional statement tests FALSE and the 
ªstopº command is executed.

See also
step
continue

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set
The set command creates one or more user-defined variables. When used without 
any arguments, the set command returns a list of all user-defined variables. Note 
that a command-line reference to a user-defined variable must be preceded by a 
dollar sign ($). 

[ Excluded figure or table. ]
If Tcl commands are enabledÐand this is the defaultÐthen the 
Tcl set command described in Appendix F is used, not this one.

Usage
SET [ <variable_name> <value> ] 

Arguments
-<variable_name>
Specifies a user-defined variable name. Optional. 
-<value>
Sets the value of a user-defined variable. Optional. 

Examples
set var "rest of line" 
Creates a user-defined variable named var with the value ªrest of line.º The 
variable var may be referenced in a command by preceding it with a dollar sign as 
in the following example:
echo ªvar = $varº
This echo command (above) produces the following:
var = rest of line

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set_tcl_escapes
When Tcl escapes are enabled (see tcl_escapes), the set_tcl_escapes command 
can be used to specify escape characters that will be ignored for VHDL extended 
identifiers, and thus allowed special meaning to the Tcl interpreter. You can also 
do this with the TclEscapeString variable

Usage
SET_TCL_escapes <string> 

Arguments
-<string>
Characters in the string will set a list of escape characters that will be ignored 
for extended identifier beginning, allowing Tcl to interpret however it wants. 
The default value of the string is ª^$*?[]abfnrtvxº which allows Tcl to 
interpret
\^  \$  \*  \?  \[  \]  \a  \b  \f  \n  \t  \v  \x
as it wants to.
Note that \\ and \" will still be reserved for Tcl.

See Also
tcl_escapes
TclEscapeString
Appendices E and F

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shift
The shift command shifts macro parameter values down one place, so that the 
value of parameter $2 is assigned to parameter $1, the value of parameter $3 is 
assigned to $2, etc. The previous value of $1 is discarded. 
The shift command and macro parameters are used in macro files. If a macro file 
requires more than nine parameters, they can be defined using the do command 
and accessed using the shift command.
To determine the current number of macro parameters, use the argc variable.

Usage
SHIfta

Example
shift
For a macro file containing nine macro parameters defined as $1 to $9, one shift 
command shifts all parameter values one place to the left. If more than nine 
parameters are named, the value of the tenth parameter becomes the value of $9 
and can be accessed from within the macro file.

See also
do

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show
The show command lists signals and subregions visible from the current signal 
environment. The show command returns its results as a Tcl string.

Usage
SHOW [ <pathname> ] [-Quiet]

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

Arguments
-<pathname>
Specifies the pathname of a signal environment for which you want the signals 
and subregions to be listed. Optional; if omitted, the current signal 
environment is assumed. 

Examples
show
List the names of all signals and subregions visible in the current signal 
environment.
show /uut
List the names of all the signals and subregions visible in the signal environment 
named /uut.
show sub_region
List the names of all the signals and subregions visible in the signal environment 
named sub_region which is directly visible in the current signal environment.

See also
environment
find

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source
The source command displays a VHDL source file in the Source window. This 
command is used to set a breakpoint in a file other than the one currently 
displayed in the Source window.

Usage
SOUrce [ <filename> ]

Arguments
-<filename>
Specifies a relative or full pathname.
If filename is omitted, then the source file for the current design context is 
displayed.

Examples
sou design.vhd
source /old/design.vhd

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splitio
The splitio command operates on a VHDL inout port to create a new signal 
having the same name as the port suffixed with ª__oº. The new signal mirrors the 
output driving contribution of the inout port.

Syntax
splitio [-r] <port_name>...

Arguments
±rSpecifies that the port selection occurs recursively into 
subregions. Optional; if omitted, included ports are limited to the 
current region.
<port_name>
Specifies the VHDL inout port. Multiple ports may be specified 
by separating names with spaces.

Description
The splitio command operates only on inout ports and silently ignores any other 
signals specified. The new signals created may be specified in any qhsim 
commands that operate on signals. These signals appear to be out ports to the 
signal selection options on qhsim commands. For example,
list -r -out /* 
selects all out ports in the design including any signals created by the splitio 
command.

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Examples
Some examples of using splitio follow:
To split inout ports, only at the current scope level:
splitio *
To split inout ports at the current scope and within all hierarchy below:
splitio -r *
To split inout ports starting with the pattern count at the current scope level:
splitio count*
To split particular ports:
splitio /u2/probe /u2/mod2/monitor tester
The splitio command can be executed at any time within the simulation session. If 
the designer plans on creating a VCD file, this command must be executed 
beforehand. While executing splitio is allowed multiple times within the 
simulation session, executing this command between runs is not recommended, 
because the new signals will not be available in the VCD file.

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status
The status command lists all current interrupted macros. The listing shows the 
name of the interrupted macro, the line number at which it was interrupted, and 
prints the line itself.
The status command returns its results as a Tcl string.

Usage
STAtus [-Quiet]

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

Examples
The transcript below contains examples of pause and status commands.
QHSIM (pause) 4> status
# Macro resume_test.do at line 3 (Current macro)
#     command executing: "pause"
#     is Interrupted
#     ONBREAK commands: "resume"
# Macro startup.do at line 34
#     command executing: "run 1000"
#     processing BREAKPOINT
#     is Interrupted
#     ONBREAK commands: "resume"
QHSIM (pause) 5> resume
# Resuming execution of macro resume_test.do at line 4

See also
pause
resume
continue

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step
The step command steps to the next VHDL statement. Procedures and functions 
can optionally be skipped. Time advances to the next scheduled activity.

Usage
STEP [ ±Over ]  [ n ]

Options
-±Over
Specifies that procedures and functions are to be executed but treated as simple 
statements instead of entered and traced line by line. Optional. 

Arguments
-n
Any integer. Optional. 

See also
run
continue

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stop
The stop command is used with the when command to stop simulation in batch 
files. The stop command has the same effect as hitting a breakpoint.
If you enter resume at the command line, the macro will resume execution with 
the when command. If you want the execution to resume automatically, put this 
command:
onbreak {resume}
At the top of your macro file.

Usage
STOP 

See also
when

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system
The system command allows you to run a UNIX shell command. This command 
can be used to copy files, check memory usage, etc. With Tcl, output will appear 
in the window, and with command substitution can be piped into other commands. 
Without Tcl, any output from the command will appear in the window you used to 
invoke the simulator, not in the Transcript window.
Variable substitution will look for UNIX environment variables before it looks for 
user-defined variables.
Wildcard characters in system command arguments are not supported.

Usage
SYStem

Examples
sys cp vector2.dat vectors.dat
Copies the file vector2.dat to vectors.dat.
sys cp $MGC_HOME/shared/pkgs/quickhdl/examples/counter.vhd .
Copies the file at $MGC_HOME/shared/pkgs/quickhdl/examples/counter.vhd to 
the current directory.

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tb
The tb (traceback) command displays a stack trace for the current process in the 
Transcript window. This lists the sequence of VHDL function calls that have been 
entered to arrive at the current state for the active process.
The tb command returns its results as a Tcl string.

Usage
TB [-Quiet]

Options
--Quiet
Keeps the output from appearing on the screen (no echo). Optional. 

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tcl_escapes
The tcl_escapes command is used to turn on and off the Tcl escape characters. 
This can also be done with the UseTelEscapes variable.

Usage
TCL_escapes [  ON | OFF  ]

Arguments
-ON
Specifies that Tcl use the set of characters as escape characters set as the 
default string or specified by the set_tcl_escapes command.
-OFF
Turns off all Tcl escape characters, which allows VHDL extended identifiers 
to start with any printable character as specified by the VHDL 1993 language 
specification.

See also
set_tcl_escapes
UseTclEscapes
Appendices E and F

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toggle add
The toggle add command enables collection of toggle statistics for the specified 
nodes. The allowed nodes are Verilog nets and VHDL signals of type bit, 
bit_vector, std_logic, and std_logic_vector (other types are silently ignored).

Syntax
toggle add 
[ ±all ] [ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ] <node_name>...

Description
See ªDescription of Toggle Checkingº on page 8-86

Arguments
±allEnables toggle statistic collection for all nodes. Optional.
±rSpecifies that toggle statistic collection is enabled recursively into 
subregions. Optional; if omitted, toggle statistic collection is 
limited to the current region.
±inEnables toggle statistic collection on nodes of mode IN. Optional.
±outEnables toggle statistic collection on nodes of mode OUT. 
Optional.
±inoutEnables toggle statistic collection on nodes of mode INOUT. Opt.
±internalEnables toggle statistic collection on internal items. Optional.
±portsEnables toggle statistic collection on nodes of modes IN, OUT, or 
INOUT. Optional.
<node_name>
Enables toggle statistic collection for the named node.

See also
ªToggle Checkingº on page G-13

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toggle reset
The toggle reset command resets the toggle counts to zero for the specified nodes.

Syntax
toggle reset
[ ±all ] [ ±r ] [ ±in ] [ ±out ] [ ±inout ] [ ±internal ] [ ±ports ] <node_name>...

Description
See ªDescription of Toggle Checkingº on page 8-86

Arguments
±allResets toggle statistic collection for all nodes that have toggle 
checking enabled. Optional.
±rSpecifies that toggle statistic collection is reset recursively into 
subregions. Optional; if omitted, the reset is limited to the current 
region.
±inResets toggle statistic collection on nodes of mode IN. Optional.
±outResets toggle statistic collection on nodes of mode OUT. 
Optional.
±inoutResets toggle statistic collection on nodes of mode INOUT. 
Optional.
±internalResets toggle statistic collection on internal items. Optional.
±portsResets toggle statistic collection on nodes of modes IN, OUT, or 
INOUT. Optional.
<node_name>
Resets toggle statistic collection for the named node.

See also
ªToggle Checkingº on page G-13

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toggle report
By default the toggle report command displays to screen a list of all nodes that 
have not transitioned to both 0 and 1 at least once. Also displayed is a summary of 
the number of nodes checked, the number that toggled, the number that didn©t 
toggle, and a percentage that toggled.

Syntax
toggle report
[ ±file <filename> ] [ ±summary ] [ ±all ]

Description of Toggle Checking
Toggle checking counts the number of transitions to 0 and 1 on specified nodes. 
Once the nodes have been selected, a toggle report may be requested at any time 
during the simulation. The toggle commands can be used on VHDL and Verilog 
designs.

Arguments
±file <filename>
Specifies a file to write the report to. If this option is selected, the 
±summary Selects only the summary portion of the report. Optional.
±all Lists all nodes checked along with their individual transition to 0 
and 1 counts. Optional.

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Reporting Format
The default report for toggle checking will look like the following:
#
 # Toggle Report                       Node    ->0    ->1
 # --------------------------------------------------------
 #                                    /b(3)      2      0
 #                                    /b(2)      0      2
 #                                    /b(1)      1      0
 #                                    /b(0)      0      1
 #                                    /d(3)      0      1
 #                                    /d(2)      0      0
 #                                    /d(1)      0      1
 #                                    /d(0)      0      0
 #                                   /by(3)      2      0
 #                                   /by(2)      0      2
 #                                   /by(1)      1      0
 #                                   /by(0)      0      1
 #                                   /dy(3)      0      1
 #                                   /dy(2)      0      0
 #                                   /dy(1)      0      1
 #                                   /dy(0)      0      0
 # --------------------------------------------------------
 #
 # Total Node Count     =      20
 # Toggled Node Count   =       4
 # Untoggled Node Count =      16
 #
 # Toggle Coverage      =   20.00 %
 #
Checkpoint/Reset. When the designer checkpoints the design the toggle file will 
be closed (if one was open). When a designer resets the simulator the toggle 
checking mode will not be retained and the toggle statistics will be cleared from 
memory.

See also
ªToggle Checkingº on page G-13

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transcript
The transcript command controls echoing of commands executed in a macro file. 
If no option is specified, the current setting is reported.

Usage
TRANscript [ ON | OFF ]

 
Arguments
-ON
Specifies that commands in a macro file will be echoed to the Transcript 
window as they are executed.
-OFF
Specifies that commands in a macro file will not be echoed to the Transcript 
window as they are executed.

Examples
tran on
Causes commands within a macro file to be echoed to the Transcript window as 
they are executed.
transcript
If issued immediately after the previous example, the message:
Macro transcripting is turned on.
would appear in the Transcript window.

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vcd add
The vcd add command adds the specified items to the VCD file. The allowed 
items are Verilog nets and variables and VHDL signals of type bit, bit_vector, 
std_logic, and std_logic_vector (other types are silently ignored). All vcd add 
commands must be executed at the same simulation time. The specified items are 
added to the VCD header and their subsequent value changes are recorded in the 
VCD file.
Related Verilog task: $dumpvars

Syntax
vcd add [-r] [-in] [-out] [-inout] [-internal] [-ports] <item_name>...

Arguments
±rSpecifies that signal and port selection occurs recursively into 
subregions. Optional; if omitted, included signals and ports are 
limited to the current region.
±inIncludes ports of mode IN. Optional.
±outIncludes ports of mode OUT. Optional.
±inoutIncludes ports of mode INOUT. Optional.
±internalIncludes internal items. Optional.
±portsIncludes all ports of modes IN, OUT, or INOUT. Optional.
<item_name>
Specifies the Verilog or VHDL item to add to the VCD file. 
Multiple items may be specified by separating names with spaces.

See also
ªValue Change Dump (VCD) Filesº on page 11-1 for more info on VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

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vcd checkpoint
The vcd checkpoint command dumps the current values of all VCD variables to 
the VCD file. While simulating, only value changes are dumped.
Related Verilog task: $dumpall

Syntax
vcd checkpoint

Arguments
None.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
Verilog tasks are documented in the IEEE 1364 standard.

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vcd comment
The vcd comment command inserts the specified comment in the VCD file.

Syntax
vcd comment <ªcomment stringº>

Arguments
<ªcomment stringº>
Comment to be included in the VCD file. Comment string must 
be in quotes if it contains any white space.

Examples
vcd comment ªThis is my first commentº
vcd comment this_is_comment_2

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files.

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vcd file
The vcd file command specifies the file name and state mapping for the VCD file 
created by a vcd add command. The vcd file command is optional. If used, it must 
be issued before any vcd add commands.
Related Verilog task: $dumpfile

Syntax
vcd file [<filename>] [±nomap] [±map <mapping pairs>] [±direction]

Arguments
<filename>Specifies the name of the VCD file that is created (the default is 
dump.vcd). Optional.
±nomap Affects only VHDL signals of type std_logic. Optional. It 
specifies that the values recorded in the VCD file shall use the 
std_logic enumeration characters of UX01ZWLH-. This results in 
a non-standard VCD file because VCD values are limited to the 
four state character set of x01z. By default, the std_logic 
characters are mapped as follows:
Table 8-3. Mapping of std_logic to VCD
VHDL
VCD
U
x
X
x
0
0
1
1
Z
z
W
x
L
0
H
1

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Table 8-3. Mapping of std_logic to VCD
±
x
±map <mapping pairs>
Affects only VHDL signals of type std_logic. Optional. It allows 
you to override the default mappings. The mapping is specified as 
a list of character pairs. The first character in a pair must be one of 
the std_logic characters UX01ZWLH- and the second character is 
the character you wish to be recorded in the VCD file. For 
example, to map L and H to z: 
vcd file -map "L z H z".
±directionAffects only VHDL ports. Optional. It specifies that the variable 
type recorded in the VCD header for VHDL ports shall be in, out, 
or inout (the default is wire). This results in a non-standard VCD 
file, but is necessary if the VCD file is to be used to stimulate a 
VHDL design with the qhsim -vcdread command.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

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vcd flush
The vcd flush command flushes the contents of the VCD file buffer to the VCD 
file. 
Related Verilog task: $dumpflush

Syntax
vcd flush

Arguments
None.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

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vcd limit
The vcd limit command specifies the maximum size of the VCD file (by default, 
limited to available disk space). When the size of the file exceeds the limit, a 
comment is appended to the file and VCD dumping is disabled.
Related Verilog task: $dumplimit

Syntax
vcd limit <filesize>

Arguments
<filesize>Specifies the maximum VCD file size in bytes.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

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vcd off
The vcd off command turns off VCD dumping and records all VCD variable 
values as x.
Related Verilog task: $dumpoff

Syntax
vcd off

Arguments
None.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

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vcd on
The vcd on command turns on VCD dumping and records the current values of all 
VCD variables. By default, vcd on is automatically performed at the end of the 
simulation time that the vcd add commands are performed.
Related Verilog task: $dumpon

Syntax
vcd on

Arguments
None.

See also
See ªValue Change Dump (VCD) Filesº on page 11-1 for more information on 
VCD files. 
Verilog system tasks are documented in the IEEE 1364 standard.

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view
The view command opens one or more of the windows.

Usage
VIEW    [ -ICON ] [DATAFLOW] [ LIST ] [ PROCESS ] [ SIGNALS ] 
[ SOURCE ] [ STRUCTURE ] [ VARIABLES ] [ WAVE ]

Option
--ICON
Allows you to iconize a specified window (you can use -icon * to iconize all 
windows.)

Arguments
-*
Wildcards can be used, for example: l* (List window), s* (Signal, Source, and 
Structure windows), even * alone (all windows).
-DATAFLOW
Opens the Dataflow window.
-LIST
Opens the List window.
-PROCESS
Opens the Process window.
-SIGNALS
Opens the Signal window.
-SOURCE
Opens the Source window.
-STRUCTURE
Opens the Structure window.

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-VARIABLES
Opens the Variable window.
-WAVE
Opens the Wave window.

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wave
The wave command adds signals to the Wave window.

Usage
WAVE [ [ ±Recursive ] [ ±IN ] [ ±OUT ] [ ±INOut] [ ±INTernal ]
[ ±Ports ] [ ±<radix> ] [ ±<format> ] 
[ ±Height<pixels> ] [ Color <standard_color_name> ]  
[ ±NOupdate ] [ ±OFFset <n> ] [ ±Scale <n> ] 
[ <signal_name> ] ¼ ] ¼

Arguments
-±Recursive
For use with wild card searches. Specifies that the scope of the search is to 
descend recursively into subregions; if omitted, the search is limited to the 
selected region.
-±IN
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode IN if they match the signal_name specification.
-±OUT
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode OUT if they match the signal_name specification.
-±INOut
For use with wild card searches. Specifies that the scope of the search is to 
include signals of mode INOUT if they match the signal_name specification.
-±INTernal
For use with wild card searches. Specifies that the scope of the search is to 
include internal signals if they match the signal_name specification.
-±Ports
For use with wild card searches. Specifies that the scope of the listing is to 
include signals of modes IN, OUT, or INOUT.

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-±<radix>
Specifies the radix for the signals that follow in the command.Valid entries 
are:
BINary
OCTal
DECimal (default for integers)
HEX
If no radix is specified for an enumerated type, a SYMBOLIC representation is 
used by default. In this representation, the actual values of the enumerated type 
of the specified signal(s) are displayed. 
If you specify a radix for an array of an enumerated type, QuickHDL converts 
each signal value to 1, 0, Z, or X. This translation is specified by the List1, 
List0, and ListZ lines in the quickhdl.ini file. For example, the value R1 would 
be mapped to 1 in the List1 line in the quickhdl.ini file, as follows:
List1 `1' TRUE R1
Any value that is not included in List1, List0, or ListZ is reported as an 
unknown (X).
-±<format> 
Specifies type of signals:
LIteral
LOgic
Analog
Literal waveforms are displayed as a box containing the signal value. Logic 
signals may be 1, 0, X, or Z. Analog signals are sized by ±scale and by ±offset.
Other signal values (i.e. L, H, U) must be mapped to these with the list 
translation specified in the quickhdl.ini file.
-±Height <pixels>
Specifies the height of the waveform (in number of pixels). 
-±Color <standard_color_name>
Specifies the color used to display a signal.These are the standard X Window 
color names; use quotes about 2-word names (ªlight blueº). Optional. 

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-±NOupdate
Appears in do files; specifies not to write to the Wave window as a signal is 
added to the window.
-±OFfset n
Modifies an analog signal's position on the display.
-±Scale n
Scales analog signals.
-<signal_name>
Specifies the name of a signal to be included in the Wave window display. 
Wildcard characters are allowed.

Examples
wave -logic -color gold out2
Displays a signal named out2. The signal is specified as a logic signal presented in 
gold.

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when

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The when command is not available for Verilog for this release. It 
will be provided in a subsequent release. 
The when command allows you to instruct the simulator to perform actions when 
the specified conditions are met; for example, you can use the when command to 
break on a signal value. Use the nowhen command to deactivate when 
commands. The when command uses a when_condition_expression to 
determine whether or not to perform the action. 
The when command uses a when_condition_expression to determine whether or 
not to perform the action. The when_condition_expression uses a simple 
restricted language (that is not related to Tcl) which permits only four operators 
and operands that may be either signal names, signame'event, or constants. The 
condition is evaluated by qhsim every time any signal in the condition changes, 
hence the restrictions. 

Usage
[<label>:] WHEN { <when_condition_expression> } { <command> ¼ }

Arguments
-<label>:
Used to identify individual when commands.
-<when_condition_expression>
Specifies the conditions to be met for the specified <command> to be 
executed.
The condition can be a signal name, in which case the curly braces can be 
omitted. The command will be executed when the signal changes value.
The condition can be an expression with these operators:
 Name
Operator
equals
==, =
The operands may be signal names, signame'event, or constants. 
Subexpressions in parentheses are permitted. The command will be executed 
when the expression is evaluated as TRUE or 1.

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 Name
Operator
not equal
!=, /=
&&, AND
OR
||, OR
The formal BNF syntax is:
condition ::= Name | { expression }
expression ::=  expression AND relation
              | expression OR relation
              | relation
relation ::= Name = Literal
           | Name /= Literal
           | Name © EVENT
           | ( expression )
Literal ::= ©<char>© | ª<bitstring>º | <bitstring>
-<command>
Can be any simulator or Tcl command or series of commands. The command 
sequence usually contains the stop command that sets a flag to break the 
simulation run after the command sequence is completed. In the Tcl mode, 
multiple-line commands can be used.

Examples
The when command below instructs the simulator to display the value of signal c 
in binary format when there is a clock event, the clock is 1, and the value of b is 
01100111, and then to stop.
when1: when {clk'event and clk='1' and b = ª01100111º}{
echo ªSignal c is [exa -bin c]
stop }

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The when command below is labeled ªaº and will cause the simulator to echo the 
message ªb changedº whenever the value of the signal b changes.
a: when b {echo ªb changedº}
The multi-line when command below does not use a label and has two conditions. 
When the conditions are met, an echo and a stop command will be executed.
when {b = 1
 and c /= 0 } {
 echo ªb is 1 and c is not 0º
 stop
}

See also
stop

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where
The where command displays information about the system environment. This 
command is useful for debugging problems where the simulator cannot find the 
required libraries or support files.
The where command returns its results as a Tcl string.

Usage
WHERE [-Quiet]

Arguments
--Quiet
Keeps the output from appearing on the screen.

Description
The where command displays three important system settings:
-current directoryÐThis is the current directory that the simulator was 
invoked from, or was specified on the simulator command line. Once in the 
simulator the current directory cannot be changed.
-current projectÐThis is the initialization file the simulator is using. All 
library mappings, window positions, and other parameters are taken from 
here.
-work libraryÐThis is the library that the simulator used to find the current 
design unit that is being simulated.

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write list
The write list command records the contents of the List window in a list output 
file. This file contains simulation data for all signals displayed in the List window.

Usage
WRITE LIST <filename>

Arguments
-LIST
Specifies that the contents of the List window are to be recorded.
-<filename>
Specifies the name of the output file where the data is to be written.

Examples
write list alu.lst
Saves the current data in the List window in a file named alu.lst.

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write report
The write report command prints a summary of the design being simulated 
including a list of all design units (configurations, entities, and packages) with the 
names of their source files.

Usage
WRITE REPORT  <filename>

Arguments
-<filename>
Specifies the name of the output file where the data is to be written. Optional; 
if omitted, the report is written to the Transcript window. 

Examples
write report alu.rep
Saves information about the current design in a file named alu.rep.

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write tssi
The write tssi command records the contents of the List window in a ªTSSI 
formatº file. The file contains simulation data for all signals displayed in the List 
window which can be converted to TSSI format. A signal definition file is also 
generated.

Usage
WRITE TSSI <filename>

Arguments
-TSSI
Specifies that the contents of the List window are to be recorded in TSSI 
format.
-<filename>
Specifies the name of the output file where the data is to be written.

Description
If the <filename> has a file extension (e.g., listfile.lst), then the signal definition 
file is given the same file name with the extension .def (e.g., listfile.def). The 
values in the listfile are produced in the same order that they appear in the list 
window. The directionality is determined from the port type if the signal is a port, 
otherwise it is assumed to be bidirectional (VHDL mode INOUT).
ªTSSI formatº is documented in the Summit Design document TDS Getting 
Started Guide, Vol. 1, R7.0, 1994. In that document, this format is called Standard 
Events Format (SEF). Table 8-4 summarizes the SEF state characters. 
Table 8-4. TSSI Standard Events Format (SEF) Characters
Input 
Output 
Bidirectional 
D =Force low 
L = Expect low
0 = Unknown direction 
low 
U = Force high 
H = Expect high
1 = Unknown direction 
high 
N = Force unknown 
X = Expect unknown
? = Unknown direction 
and level 

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Table 8-4. TSSI Standard Events Format (SEF) Characters
Input 
Output 
Bidirectional 
Z = Force high impedance 
T = Expect high 
impedance
F = Unknown direction 
high impedance
Signals that can be converted to SEF are enumerations with 255 or fewer 
elements. The nine enumeration values defined in the IEEE Standard 1164 
std_ulogic (U, X, 0, 1, Z, W, L, H, and -) are converted to SEF values 
according to Table 8-5. Any other values besides these nine are converted to X 
and cause an error message. Though the WRITE TSSI command was 
developed for use with std_ulogic, any signal type that uses only the values 
defined for std_ulogic (which includes the VHDL standard type bit) will be 
converted to SEF values. 
Table 8-5. std_ulogic to SEF Conversions
std_ulogic 
State
Characters
SEF State Characters
Input 
Output 
Bidirectional 
U
N 
X
? 
X
N 
X
? 
0
D 
L
0
1
U 
H
1
Z
Z 
T
F 
W
N 
X
? 
L
D 
L
0
H
U 
H
1
-
N
X
? 
Bidirectional logic values are not converted because only the resolved value is 
available. The TSSI ASCII In Converter and ASCII Out Converter can be used 
to resolve the directionality of the signal and to determine the proper forcing or 
expected value on the port. Lower case values x, z, w, l and h are converted to 
X, Z, W, L, and H, respectively. Any other values will cause an error message 
to be generated the first time an invalid value is detected on a signal; the value 
will be converted to a question mark (?).

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See also
tssi2mti

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write wave
The write wave command records the contents of the Wave window in PostScript 
format. The output file can then be printed on a PostScript printer.

Usage
WRITE WAVE <filename>

Arguments
-WAVE
Specifies that the contents of the Wave window are to be recorded. Required. 
-<filename>
Specifies the name of the PostScript output file. Required. 

Examples
write wave alu.ps
Saves the current data in the Wave window in a file named alu.ps.
For more flexibility when creating a PostScript waveform output file, use the 
Wave window PostScript dialog box