The LogicLock tutorial module uses the Altera-provided largefilter and filter projects to teach you how to use the LogicLock feature. These projects (and their associated files) are installed on your computer during the Quartus II installation process. The top-level 16-tap largefilter design instantiates four instances of the 4-tap filter design entity. For convenience, the filter design entity has already been isolated in the filter project.
This section guides you through the steps necessary to open and compile the top-level largefilter design and view the non-optimized timing analysis results to obtain a baseline timing performance. Subsequent sections teach you how to use LogicLock constraints to optimize the filter design entity, and then import the LogicLock constraints into the top-level largefilter project.
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