LogicLock placement constraints allow you to optimize each block of a hierarchical design, then lock down the relative placement of the block so that the block's performance is preserved during subsequent compilations or for use in a larger design. You can save the optimized synthesis results in a Verilog Quartus Mapping File (.vqm) in order to properly export the block from one project to another.
This tutorial section shows you how to direct the Compiler to save the synthesis results of the filter design entity in a VQM File following compilation. You can then use the VQM File to import the logic of the optimized block into the top-level largefilter design.
|