Timing Analysis Module

With the Quartus II Timing Analyzer, you can analyze the timing performance of all logic in your design. You can trace signal paths and locate them in the Floorplan Editor, determining critical speed paths that limit the design's performance.

The Quartus II Timing Analyzer runs automatically at the end of the compilation process, or you can run the Timing Analyzer separately after first-time project compilation. When timing analysis is complete, timing information is reported in the Timing Analyses folder of the Compilation Report.

The Timing Analysis tutorial module guides you through the steps necessary to view the timing analysis results in the Compilation Report window, specify timing requirements, perform multiclock timing analysis, and assign a multicycle path.

If you did not sequentially complete the Design Entry and Compilation tutorial modules before starting this module, open and compile the timing analysis project. If you already sequentially completed the Design Entry and Compilation tutorial modules, proceed to Section 1: View Timing Analysis Results.

Open & Compile the Timing Analysis Project

If you have not already sequentially completed the Design Entry and Compilation tutorial modules, you must first open and compile the timing analysis project before you can begin working in the Timing Analysis tutorial module.

To open the timing analysis project, follow these steps:

1. Choose Open Project (File menu). The Open Project dialog box appears.

2. In the \qdesigns\fir_filter\timing subdirectory, select the Altera-provided timing_fir_filter.quartus project file in the Files list.

3. Click Open.

4. Choose Start Compilation (Processing menu). The Compiler compiles the design.

5. When you receive a message indicating that compilation was successful, click OK.

Section 1: View Timing Anlysis Results

After you compile a design, you can view the timing analysis results in the Compilation Report. By default, the Timing Analyzer reports the maximum frequency (f_MAX) of every register, the worst-case register-to-register delays, the input setup (t_SU) and input hold (t_H) times of every input register, the clock-to-output (t_CO) delays of every output register, and the pin-to-pin (t_PD) delays between all pins. In addition, you can customize the timing analysis by specifying timing requirements and other options.

Step 1: View the f_MAX Timing Analysis Report

The fmax section of the Compilation Report shows the frequency requirements and worst-case speed performance of your design.

To open the fmax section of the Compilation Report, follow these steps:

1. If necessary, to open the Compilation Report, choose Compilation Report (Processing menu).

2. In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.

3. Under the Timing Analyses folder, select the fmax section. The f_MAX information appears in a table.

4. To expand the list and display the destination registers associated with the clock, click the + icon next to the clk clock name. By default, the list expands to show the 10 slowest destination registers.

	You can go to "Specifying Timing Analysis Reporting Restrictions" in Quartus II Help for information about customizing timing analysis reporting.

Step 2: List the f_MAX Timing Paths

To list the f_MAX timing paths, follow these steps:

1. To expand the list and display the source registers feeding a destination register, click the + icon to expand the first destination register name in the fmax section. By default, the list expands to show the 10 slowest source registers.






2. Select the first source register name in the list.

3. Choose List Paths (right button pop-up menu). The delay paths for the source register, including intermediate delay paths, appear as messages in the System tab of the Messages window.

4. In the Messages window, click the + icon to expand the Clock <name> has Internal fmax of message. The Longest register to register delay, Smallest Clock skew, Micro clock to output delay, and Micro setup delay messages are displayed.






5. Click the + icon to expand the Longest register to register delay message. The intermediate time increments used to calculate the timing path delay are displayed.

Step 3: Locate a Timing Path in the Floorplan Editor

To locate the source of a timing path message in the Last Compilation floorplan, follow these steps:

1. In the Messages window, select the Longest register to register message.

2. Choose Locate (right button pop-up menu). The data path is highlighted in the floorplan, and the total timing path delay appears alongside the path.

Step 4: View the t_SU Timing Analysis Report

The tsu section of the Compilation Report displays the actual setup time t_SU for the input pins that feed the data or clock enable inputs to the destination register.

To open the tsu section of the Compilation Report, follow these steps:

1. In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.

2. Under the Timing Analyses folder, select the tsu section. The input setup time information is displayed in a table.

3. To expand the list and display the register and clock name(s) associated with the data pin, click the + icon.

4. When you are finished viewing the paths, choose Close (File menu).

	You can also view other sections in the Compilation Report by modifying the procedures above. Specific steps for viewing all timing analysis results are described in "Viewing Timing Analysis Results in the Report Window" in Quartus II Help.

Section 2: Specify Timing Requirements

Timing requirements allow you to specify the desired speed performance for the entire project, for specific design entities, or for individual nodes and pins. For example, you can specify project-wide timing requirements for the setup time (t_SU), hold time (t_H), clock-to-output delay (t_CO), pin-to-pin delays (t_PD), and maximum frequency (f_MAX).

In addition, you can override the default timing requirements on specific portions of the design by making individual timing assignments. You can also assign other individual timing assignments to cut timing paths, add external input or output delays, and invert clocks to further optimize your design. If you specify both individual and project-wide timing requirements, the Compiler uses the most stringent requirements.

You can specify timing requirements for the entire project with the Timing Settings command (Assignments menu), or you can specify timing requirements for individual entities, nodes, and pins with the Assignment Organizer command (Assignments menu). If you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals when you use timing-driven compilation.

The following procedures explain how to specify timing requirements and other timing analysis settings using menu commands and dialog boxes. However, you can also easily specify timing requirements and other timing analysis settings by following the steps in the Timing Wizard (Assignments menu).

Step 1: Specify the Default Required f_MAX

You can specify a default f_MAX for an entire project, or you can specify a required f_MAX for selected portions of the project.

To specify the default required f_MAX, follow these steps:

1. Choose Timing Settings (Assignments menu). The Timing Settings page of the Settings dialog box appears.

2. In the Category list, select Clocks under Timing Settings. The Clocks page appears.

3. Under Specify circuit frequency as, Make sure Default required fmax is selected.

4. In the Default required fmax box, type 45 and select MHz in the list. The Fitter will now optimize the placement of logic in the device in order to meet this timing goal, and the Timing Analyzer reports any signals that do not acheieve the f_MAX requirement during compilation.

You can override this default required fMAX for individual clocks in your design by creating clock settings and assigning them to individual clock signals in your design. This procedure is described later in this tutorial.

Step 2: Cut Timing Paths

You can direct the Timing Analyzer to ignore specific signal paths by cutting them from the timing analysis. You can turn on options in the Other Requirements & Options page (Settings dialog box) to cut all instances of specific categories of paths, or you can cut specific paths on a node-by-node basis with the Cut Timing Path assignment in the Assignment Organizer (Assignments menu).

To globally cut off feedback from I/O pins, follow these steps:

1. In the Settings dialog box, select Other Requirements & Options under Timing Settings. The Other Requirements & Options page appears.

2. Make sure Cut off feedback from I/O pins is turned on. The Timing Analyzer will now ignore all signal feedback from within the device.

3. Click OK.

Section 3: Perform Multiclock Timing Analysis

The Quartus II Timing Analyzer automatically performs single-clock frequency analysis as part of compilation. However, the Timing Analyzer can also perform timing analysis on designs that use complex timing assignments, such as designs with multiple clocks.

To perform an accurate multiclock analysis, you must first define the relationship between all clocks in the design. To define this relationship, you must specify which signals function as the absolute clocks (not dependent on other clocks) and the derived clocks (dependent on other clocks) in the design. In the Quartus II software, you define the behavior and requirements of clocks by creating clock settings. Then, you assign these settings to the clock signals in the design.

Step 1: Create Absolute Clock Settings

To create absolute clock settings, follow these steps:

1. Choose Timing Settings (Assignments menu). The Timing Settings page of the Settings dialog box appears.

2. In the Category list, select Clocks under Timing Settings. The Clocks page appears.

3. Under Specify circuit frequency as, select Settings for individual clock signals.

4. Click New. The New Clock Settings dialog box appears.

5. In the Clock settings name box, type clocka as the name for the new group of clock settings.

6. To specify that these clock settings are for an absolute clock, under Relationship to other clock settings, make sure Independent of other clock settings is selected.

7. To specify the required f_MAX of the absolute clock, in the Required fmax box, type 50 and select MHz in the list.






8. Click OK. The clocka settings appear in the Existing clock settings list.

Step 2: Create Derived Clock Settings

To create derived clock settings, follow these steps:

1. In the Clocks page, click New. The New Clock Settings dialog box appears.

2. In the Clock settings name box, type clockb.

3. Under Relationship to other clock settings, select Based on and select clocka in the list.

4. To specify timing requirements for the derived clock, click Derived Clock Requirements. The Derived Clock Requirements dialog box appears.

5. To specify that the derived clock is a multiple of two of the absolute clock, select 2 in the Multiply base absolute clock fmax by list.

6. To specify that the derived clock is offset from the absolute clock, type 0.5 in the Offset from base absolute clock fmax box and select ns in the list.






7. Click OK.

8. In the New Clock Settings dialog box, click OK to add the clockb clock settings to the Existing clock settings list.

9. In the Settings dialog box, click OK.

Step 3: Assign the Clock Settings to a Pin

Once you have defined an absolute or derived clock setting, you must assign the setting to the appropriate clock signal(s) in the design. In the Quartus II software, you can use the Assignment Organizer command (Assignments menu) to create, delete, edit, and view the assignments in the project.

To assign the clocka settings to the clk pin, follow these steps:

1. Choose Assignment Organizer (Assignments menu). The By Node tab of the Assignment Organizer dialog box appears automatically.

2. Under Mode, select Edit specific entity and node settings for.






3. Under Mode, click Browse (...) next to the Name box. The Node Finder dialog box appears.

4. To find the clock signal name to which you want to assign the clock settings, in the Node Finder dialog box, select Pins: all in the Filter list and then click Start.






5. In the Nodes Found list, double-click the clk pin name.

6. To copy the clk pin name to the Assignment Organizer dialog box and close the Node Finder dialog box, click OK.

Assign the Clock Settings to a Pin (cont.)

To continue assigning the clock settings to a pin, follow these steps:

7. In the Assignment Organizer dialog box, click the + icon to expand Timing in the Assignment Categories list.

8. Click the Click here to add a new assignment text.

9. Under Assignment, in the Name list, make sure Clock Settings is selected.

10. To identify the clock settings that should be assigned to the pin, make sure clocka is selected in the Setting list.

11. Click Add. The new assignment appears in the Assignment Categories list.






12. Under Mode, click Browse (...) next to the Name box. The Node Finder dialog box appears.

13. To remove the clk pin name from the Selected Nodes list, click Remove all nodes (<<).

14. To find the clkx2 pin to which you want to assign clock settings, in the Node Finder dialog box, click Start.

15. In the Nodes Found list, double-click the clkx2 pin name.

16. To copy the clkx2 pin name to the Assignment Organizer dialog box and close the Node Finder dialog box, click OK.

17. Repeat steps 7 through 11 to assign the clockb settings to the clkx2 pin.

18. In the Assignment Organizer dialog box, click OK.

	You can also specify many other types of individual timing assignments. You can go to "Making Individual Timing Assignments" in Quartus II Help for more information on available timing assignments.

Step 4: Rerun the Timing Analysis

To rerun timing analysis:

1. Choose Start > Start Timing Analysis (Processing menu).

2. When the Quartus II software asks whether you want to recompile before starting timing analysis, click No. The timing analysis runs without recompiling the design.

The Quartus II software asks you if you want to recompile at this point because specifying timing requirements affects fitting when you are using timing-driven compilation. However, for this tutorial, recompilation is not necessary.

3. When the Quartus II software informs you that the timing analysis was successful, click OK. Note that a message appears in the Messages window indicating that timing requirements were not met.

Step 5: View the Clock Requirements Timing Analysis Section

In designs that use complex timing assignments, the Timing Analyzer generates a Clock Requirement section, rather than an fmax section, for each clock signal you designate in the design. The Clock Requirement section reports the speed performance as a "slack" value. Slack is the margin by which a timing requirement was achieved or not achieved. A positive slack value, displayed in black, indicates that the requirement was achieved. A negative slack value, displayed in red, indicates that the requirement was not achieved.

To view the Clock Requirement section for the clkx2 signal, follow these steps:

1. In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.

2. Under the Timing Analyses folder, select the Clock Requirement section for the clkx2 signal. The timing analysis information is displayed in a multi-column table. If necessary, drag the resizing tool to resize columns in the table.






The Clock Requirement section for the clkx2 signal displays slack values in red, indicating that the specified f_MAX requirement was not achieved along the path. The following section describes how to specify a multicycle path that corrects this condition.

Section 4: Specify a Multicycle Path

In the fir_filter design, the 0.5 ns offset you specified for the clockb clock settings causes the Timing Analyzer to report that timing requirements were not met. This condition was intentionally created for this tutorial in order to demonstrate how the Multicycle timing assignment affects the default setup relationship.

By default, the Timing Analyzer uses the most restrictive setup relationship when analyzing paths between registers that are clocked by different clocks. The Timing Analyzer verifies that the data is present at the destination register in time to be properly latched.

In designs with multiple clocks, for every latch edge on the destination clock, the launching edge on the source register determines the delay requirement for the path. In the fir_filter design, for every latch edge of the destination register, the Timing Analyzer finds the nearest launch edge that precedes each capture edge. The smallest difference determines the maximum delay requirement.

You can use the Multicycle timing assignment to specify a path that requires more than one clock cycle to propagate. Assigning a Multicycle of 2 to all registers clocked by clkx2 allows you to override the default setup relationship and delay the latch edge by one clock cycle, thus achieving the specified timing requirements.

Step 1: Create a Multicycle Timing Assignment

You can make individual timing assignments to a single node or to a path between a source and destination point. When you make a point-to-point assignment to the path between two clock pins, the assignment is automatically applied to all register-to-register paths between the two clocks. To add the Multicycle assignment to all register-to-register paths between the clk and clkx2 pins, follow these steps:

1. To open to the filtref.bdf block diagram, choose Open (File menu). The Open dialog box appears.

2. In the Files of type list, select Device Design Files.

3. In the Files list, select filtref.bdf.

4. Click Open.

5. In the filtref.bdf block diagram, select the clkx2 input pin.

6. Choose Assignment Organizer (right button pop-up menu). The Assignment Organizer dialog box appears, with the Edit specific entity & node settings for option selected, and with the hierarchical path name of the clkx2 pin shown in the Name box.

7. In the Assignment Categories list, click the + icon to expand Timing.

8. Click the Click here to add new assignment text.

9. Under Assignment, select Multicycle in the Name list.

10. To specify a multicycle path that requires two clock cycles to propagate, in the Setting box, type 2.

11. To specify the source point for a point-to-point assignment, in the Fed by box, type clk or click Browse (...) to select the pin name with the Node Finder dialog box.

12. Click Add. The assignment appears in the Assignment Categories list.

13. Click OK.

Step 2: Rerun Timing Analysis

To rerun timing analysis:

1. Choose Start > Start Timing Analysis (Processing menu).

2. When the Quartus II software asks whether you want to recompile before starting timing analysis, click No. The timing analysis runs without recompiling the design.

3. When the Quartus II software informs you that the timing analysis was successful, click OK. Note that a message appears in the Messages window indicating that all timing requirements were met.

Step 3: View the Clock Requirements Timing Analysis Section

To view the timing analysis results to determine how setting the Multicycle assignment affected timing requirements, follow these steps:

1. In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.

2. Under the Timing Analyses folder, select the Clock Requirement section for the clkx2 signal. The Clock Requirement section displays all slack values in black, indicating that all timing requirements were achieved after overriding the default setup relationship with the Multicycle assignment.

If you want to continue the tutorial sequentially, proceed to the Simulation module. If you want to start another tutorial module, return to Start the Tutorial.