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LogicLock Module |
LogicLock™ regions are flexible, reusable floorplanning constraints that increase your ability to guide logic placement in the target device. LogicLock regions support team-oriented, modular design by enabling you to optimize logic blocks individually. You can then import the optimized logic blocks into a larger design to preserve the optimized performance.
This LogicLock tutorial module uses an Altera®-provided hierarchical design to teach you how to use the LogicLock feature of the Quartus II software to optimize a lower-level design entity, preserve the optimized constraints and performance, and import the LogicLock constraints into the top-level design.
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This Advanced tutorial module assumes that you are familiar with the basic functionality of the Quartus II software, as described in the Basic tutorial modules. |
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The LogicLock tutorial module uses the Altera-provided largefilter and filter projects to teach you how to use the LogicLock feature. These projects (and their associated files) are installed on your computer during the Quartus II installation process. The top-level 16-tap largefilter design instantiates four instances of the 4-tap filter design entity. For convenience, the filter design entity has already been isolated in the filter project.
This section guides you through the steps necessary to open and compile the top-level largefilter design and view the non-optimized timing analysis results to obtain a baseline timing performance. Subsequent sections teach you how to use LogicLock constraints to optimize the filter design entity, and then import the LogicLock constraints into the top-level largefilter project.
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To open the largefilter top-level project, follow these steps:
Choose Open Project (File menu). The Open Project dialog box appears.
In the \qdesigns\logiclock\largefilter subdirectory, select the Altera-provided largefilter.quartus project file in the Files list.
Click Open.
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To specify the default required fMAX for the largefilter design, follow these steps:
Choose Timing Settings (Assignments menu). The Timing Settings page of the Settings dialog box appears.
In the Category list, select Clocks under Timing Settings. The Clocks page appears.
Under Specify circuit frequency as, select Default required fmax.
In the Default required fmax box, type 80 and select MHz in the list.
Click OK.
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To compile the top-level largefilter design, follow these steps:
Choose Start Compilation (Processing menu).
When you receive a message indicating that compilation was successful, click OK. A message that appears in the Messages window indicates that timing requirements were not met.
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After you compile the largefilter design, you can view the speed performance in the fmax section of the Compilation Report.
To view the pre-optimized speed performance of the largefilter top-level design, follow these steps:
In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.
Under the Timing Analyses folder, select the fmax section. The fmax section displays the worst-case speed performance of the design. The fmax section displays performance results in red, indicating that the specified fMAX requirement was not achieved in the design. Note that all performance violations are related to the multiplier operators in the design.
The following tutorial sections describe how to use the LogicLock feature to optimize the multiplier operators and achieve performance goals.
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After a successful compilation, you can view the fitting results in either the Last Compilation floorplan or the Timing Closure floorplan. The Last Compilation floorplan shows how the Compiler implemented the logic of a design into an Altera device. The Timing Closure floorplan is optimized with additional floorplanning features that allow you to view and edit LogicLock regions, in conjunction with other user assignments and Fitter placement, to help achieve timing closure.
To open the Timing Closure floorplan, follow these steps:
Choose Timing Closure Floorplan (Assignments menu). The Timing Closure floorplan appears, showing how the Compiler implemented the logic of the design.
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You can click and drag the borders of the Floorplan Editor window to resize the window as necessary. |
Choose Field View (View menu). Field View displays the major device resources in a high-level, outline view, allowing you to visualize fitting and critical timing closure components in an uncluttered format.
When you are finished looking at the Timing Closure floorplan, choose Close (File menu).
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LogicLock placement constraints allow you to optimize each block of a hierarchical design, then lock down the relative placement of the block so that the block's performance is preserved during subsequent compilations or for use in a larger design. You can save the optimized synthesis results in a Verilog Quartus Mapping File (.vqm) in order to properly export the block from one project to another.
This tutorial section shows you how to direct the Compiler to save the synthesis results of the filter design entity in a VQM File following compilation. You can then use the VQM File to import the logic of the optimized block into the top-level largefilter design.
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To open the filter project, follow these steps:
Choose Open Project (File menu). The Open Project dialog box appears.
In the \qdesigns\logiclock\filter subdirectory, select the Altera-provided filter.quartus project file in the Files list.
Click Open.
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You can direct the Compiler to save synthesis results in a VQM File following compilation. The VQM File is an ATOM-based netlist that preserves the node names when the entity is exported and synthesized in another design.
To direct the Compiler to save intermediate synthesis results, follow these steps:
Choose Settings (Assignments menu). The Settings dialog box appears.
In the Category list, select Fitting under Compiler Settings. The Fitting page appears.
Under Timing-driven compilation, make sure Optimize timing is turned on, and that Normal compilation is selected in the list.
To avoid placing registers in I/O cells when optimizing a sub-entity, turn off Optimize I/O cell register placement for timing. Turning off this option ensures that sub-entity I/Os that do not exist in the top-level design are not exported.
In the Category list, select Synthesis under Compiler Settings. The Synthesis page appears.
Turn on Save a node-level netlist into a persistent source file.
To save the filter.vqm file to the top-level project directory following compilation, type D:\qdesigns\logiclock\largefilter\filter.vqm in the File name box.
Click OK to save the settings.
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To specify the default required fMAX for the filter design, follow these steps:
Choose Timing Settings (Assignments menu). The Timing Settings page of the Settings dialog box appears.
In the Category list, select Clocks under Timing Settings. The Clocks page appears.
Under Specify circuit frequency as, select Default required fmax.
In the Default required fmax box, type 80 and select MHz in the list. This requirement matches the fMAX requirement in the top-level largefilter design.
Click OK.
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During analysis and synthesis the Compiler analyzes the design files for syntax and semantic errors, extrapolates the design hierarchy, and synthesizes the logic.
To perform analysis and synthesis on the design, follow these steps:
Choose Start > Start Analysis & Synthesis (Processing menu). The Compiler analyzes and synthesizes the design.
When you receive a message indicating that analysis and synthesis was successful, click OK.
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A LogicLock region is a type of placement constraint. You can define any arbitrary rectangular region of physical resources on the target device as a LogicLock region. You can create LogicLock regions in either the Timing Closure or Current Assignments floorplan, or in the LogicLock Regions window. By assigning nodes or entities to a LogicLock region, you direct the Compiler to place those nodes or entities inside the region during fitting. The LogicLock regions you create are displayed in the floorplan. All LogicLock regions are defined by two parameters: size and state. You can define the following three types of LogicLock regions:
| LogicLock Region Type: |
Description: |
| Fixed size, locked state | The region is defined as a specific height and width. Location is assigned to specific device resource. Locked state regions are designated by a solid border in the floorplan. |
| Fixed size, floating state | The region is defined as a specific height and width. The Quartus II software chooses the most appropriate location for the region. Floating state regions are designated by a dashed border in the floorplan. |
| Auto-size, floating state | The Quartus II software determines the optimum size and location for the region. Auto-size regions are designated by a dotted border in the floorplan. |
LogicLock regions can be nested hierarchically. Making one LogicLock region the child of another LogicLock region places the child region inside its parent region and specifies that the child's location is relative to the parent location. When you move a parent region, its child regions maintain their placement relative to the parent region.
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Nested LogicLock regions can only be created with the LogicLock Regions window. |
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To define a LogicLock region, follow these steps:
Choose Timing Closure Floorplan (Assignments menu). The Timing Closure floorplan appears.
Choose LogicLock Regions Window (Assignments menu). The LogicLock Regions window appears.
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You can undock the LogicLock Regions window at any time by clicking anywhere on the window and turning off Enable Docking (right button pop-up menu). |
To create a parent LogicLock region, double-click the <<new>> cell in the Region name column. An editable text box appears in the cell.
To name the LogicLock region, type filter in the text box and press Enter. A LogicLock region of default size and state appears in the LogicLock Regions window and in the Timing Closure floorplan.
In the LogicLock Regions window, double-click the folder icon next to the filter LogicLock region name. The Contents tab of the LogicLock Region Properties dialog box appears automatically.
Click the Size tab.
To specify that filter is a fixed size LogicLock region, select Fixed in the Size tab.
Under Settings, make sure 1 is specified in the Width box and that MegaLABs is selected in the list.
Under Settings, type 5 in the Height box.
Click Set size.
Click the Location tab.
Under State, make sure Floating is selected.
Click OK. The filter fixed size, floating state, parent LogicLock region appears in the LogicLock Regions window and Timing Closure floorplan as defined.
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To define a LogicLock region that is a child of the filter parent LogicLock region, follow these steps:
In the LogicLock Regions window, select the filter LogicLock region name in the Region name column.
Choose New (right button pop-up menu). A new child LogicLock region with the default name Region_0 appears under the filter region in the LogicLock Regions window and in the Timing Closure floorplan.
To rename the default Region_0 LogicLock region name, double-click the Region_0 cell in the Region name column. An editable text box appears in the cell.
Type mult3 in the text box to replace the default name and press Enter.
In the LogicLock Regions window, double-click the folder icon next to the mult3 LogicLock region name. The Contents tab of the LogicLock Region Properties dialog box appears automatically.
Click the Size tab.
To specify that mult3 is a fixed size LogicLock region, select Fixed under LogicLock region size.
Under Settings, make sure 1 is specified in the Width box, and that MegaLABs is selected in the list.
Under Settings, type 1 in the Height box.
Click Set size.
Click the Location tab.
Under State, make sure Floating is selected.
Click OK. The mult3 fixed size, floating state, child LogicLock region appears in the LogicLock Regions window and Timing Closure floorplan as defined.
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To define additional child LogicLock regions, follow these steps:
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Repeat steps 1 through 13 described in Step 2: Define a Child LogicLock Region to create three additional child LogicLock regions with the identical options listed in the following tables: Specify these options for the mult2 child LogicLock region:
Specify these options for the mult1 child LogicLock region:
Specify these options for the mult0 child LogicLock region:
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Assigning nodes or entities to a LogicLock region directs the Compiler to place those nodes or entities inside the region during fitting. You can assign nodes and entities to LogicLock regions by using the Assignment Organizer dialog box (Assignments menu) or by dragging and dropping them from the Node Finder or from the Compilation Hierarchies tab of the Project Navigator.
To assign logic to the LogicLock regions, follow these steps:
In the Project Navigator, click the Hierarchies tab.
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The Project Navigator appears by default when you start the Quartus II software. However, if necessary, you can display the Project Navigator by turning on Utility Windows > Project Navigator (View menu). |
In the Hierarchies tab, click the + icon to expand the filter hierarchy.
In the Hierarchies tab, select the filter design entity name.
To assign the logic of the filter design entity to the filter LogicLock region, drag the filter entity name onto the filter LogicLock region name in the LogicLock Regions window. The logic of the filter entity is now assigned to the LogicLock region.
In the LogicLock Regions window, move the mouse pointer over filter LogicLock region name. The properties of the region, including the assigned filter entity, appear in a tool tip, indicating that the logic of the filter entity is now assigned to the LogicLock region.
| Drag design entity: | To LogicLock region: |
| mult:mult_i0 | mult0 |
| mult:mult_i1 | mult1 |
| mult:mult_i2 | mult2 |
| mult:mult_i3 | mult3 |
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During compilation, the Compiler settings control design processing. The Compiler locates and processes all timing requirements and LogicLock region assignments and generates the VQM File that is necessary to preserve the design entity's performance when integrated into a larger design. When the compilation is complete, you can view the results of timing analysis in the Compilation Report.
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To compile the optimized filter design and generate the VQM File, follow these steps:
Choose Start Compilation (Processing menu).
When you receive a message indicating that compilation was successful, click OK to close the message box. A message that appears in the Messages window indicates that all timing requirements were met.
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After you compile the filter design, you can view the speed performance in the fmax section of the Compilation Report.
To view the speed performance of the optimized filter design, follow these steps:
In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.
Under the Timing Analyses folder, select the fmax section. The fMAX information appears in a table. The fmax section displays the performance information in black, indicating that the specified fMAX requirement was achieved in the design.
The final tutorial sections describe how to import LogicLock constraints to preserve this optimized performance in the top-level design.
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After a successful compilation, you can view the LogicLock fitting results in the Timing Closure floorplan. The floorplan shows how the Compiler implemented the LogicLock region constraints in the design.
To view the LogicLock regions in the floorplan, follow these steps:
Choose Timing Closure Floorplan (Assignments menu). The floorplan shows the user-defined LogicLock region, as well as how the Fitter actually implemented the floating LogicLock region in the device.
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You can click and drag the borders of the Floorplan Editor window to resize the window as necessary. |
Click the Selection and Smart Drawing Tool button 
on the toolbar.
With the Selection and Smart Drawing Tool, point to some of the used resources within the Fitter assigned LogicLock regions. The names of the signals indicate that the appropriate logic is constrained by the LogicLock regions.
When you are finished looking at the Timing Closure floorplan, choose Close (File menu).
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When you back-annotate LogicLock region constraints, the Quartus II software saves all the constraints in an ESF. This ESF preserves the size, location and member nodes of a LogicLock region. You can then export the ESF and import it into the top level design to implement the LogicLock region constraints.
The following tutorial section teaches you how to perform LogicLock back-annotation, and export the LogicLock constraints to the top-level project.
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When you are satisfied with the Compiler's implementation of a LogicLock region, you can back-annotate its size, location, and/or contents for use on subsequent compilations. Back-annotating a LogicLock region's size and location preserves the region's height, width, and contents in an ESF. Back-annotating a LogicLock region's contents preserves the relative location of each node in the region, as well as the region's size and location.
To back-annotate the size, location, and contents of all LogicLock regions in the design, follow these steps:
Choose LogicLock Regions Window (Assignments menu). The LogicLock Regions window appears.
In the LogicLock Regions window, double-click the folder icon next to the filter LogicLock region name. The Contents tab of the LogicLock Region Properties dialog box appears automatically.
Click Back-Annotate Contents and click Yes when asked to demote cell assignments. The back-annotated nodes appear in the Back-annotated Node list.
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To export the ESF containing the filter LogicLock constraints to the top-level project, follow these steps:
In the LogicLock Regions window, select the filter LogicLock region name.
Choose Export LogicLock Regions (Assignments menu). The Export LogicLock Regions dialog box appears.
In the Export focus full hierarchy path box, make sure filter is specified.
In the File name box, type D:\qdesigns\logiclock\largefilter\filter.esf or click Browse (...) to select this directory.
Click OK. The ESF is exported to the top-level project directory.
Close the LogicLock Regions window.
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To open the largefilter top-level project, follow these steps:
Choose Open Project (File menu). The Open Project dialog box appears.
In the \qdesigns\logiclock\largefilter subdirectory, select the largefilter.quartus project file in the Files list.
Click Open.
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To ensure that node names do not change when the filter design entity is synthesized in the top-level design, you must replace the original filter.edf file in the project with the filter.vqm file that you generated during incremental synthesis.
To replace the filter.edf file with the filter.vqm file in the top-level project, follow these steps:
Choose Add/Remove Files in Project (Project menu). The Add/Remove page of the Settings dialog box appears automatically.
In the File name list, select the filter.edf file.
To remove the file from the project, click Remove.
In the File name box, type filter.vqm or click Browse (...) to select the file from the \qdesigns\logiclock\largefilter subdirectory.
Click OK.
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When you import a lower-level ESF that contains LogicLock region constraints, the Quartus II software adds these constraints to the top-level ESF. In addition, the Quartus II software automatically instantiates multiple instances of the LogicLock region where appropriate. For example, when you import the LogicLock constraints for the single 4-tap filter design entity into the top-level design, the Quartus II software automatically applies the constraints to all four instances of the 4-tap filter in the largefilter design.
To prevent placement conflicts, the Compiler assigns imported parent LogicLock regions as floating locations. However, it preserves the location of any imported child regions relative to their parents.
This tutorial section teaches you how to import LogicLock constraints into the top-level project, recompile the design, and view the optimized results.
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To successfully import LogicLock constraints, you must first perform analysis and elaboration on the design. During analysis and elaboration the Compiler submits the design to the Database Builder, which analyzes the design files for syntax and semantic errors, and extrapolates the hierarchy and the instances of each design entity. The Compiler stops when the Database Builder module finishes processing the design file(s).
To perform analysis and elaboration on the design, follow these steps:
Choose Start > Start Analysis & Elaboration (Processing menu). The Compiler analyzes the design.
When you receive a message indicating that analysis and elaboration was successful, click OK.
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To import the LogicLock constraints into the top-level project, follow these steps:
Choose Import LogicLock Regions (Assignments menu). The Import LogicLock Regions dialog box appears.
Under Assignment categories, make sure Import LogicLock region assignments and other node or entity assignments is selected.
Under Assignment categories, turn off Import pin assignments.
Under LogicLock import settings, select Create new LogicLock regions and update the currently selected LogicLock region(s). If you are asked if you want to overwrite the current origin settings of the LogicLock regions with the origin settings in the imported Entity Settings File, click OK.
To import the LogicLock Regions, click OK.
Choose LogicLock Regions Window (Assignments menu). Four instances of the filter LogicLock region name appear in the LogicLock Regions window, indicating that these constraints are applied to the four identical filter design entities in the top-level design.
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To implement the imported LogicLock regions by compiling the top-level design, follow these steps:
Choose Start Compilation (Processing menu). The Compiler compiles the design.
When you receive a message indicating that compilation was successful, click OK. A message that appears in the Messages window indicates that all timing requirements were met.
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After you compile the optimized largefilter design, you can view the speed performance in the fmax section of the Compilation Report to verify the optimized performance of the the top-level design.
To view the optimized speed performance of the largefilter top-level design, follow these steps:
In the left pane of the Compilation Report window, click the + icon to expand the Timing Analyses folder.
Under the Timing Analyses folder, select the fmax section. The fmax section displays the optimized speed performance of the design. The design's performance is improved by the use of LogicLock regions.
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After a successful compilation, you can view the LogicLock fitting results in the Timing Closure floorplan. The floorplan shows how the Compiler implemented the LogicLock region constraints in the top-level design.
To view the LogicLock regions in the floorplan, follow these steps:
Choose Timing Closure Floorplan (Assignments menu). The LogicLock regions are displayed in the floorplan.
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You can click and drag the borders of the Floorplan Editor window to resize the window as necessary. |
Click the Selection and Smart Drawing Tool button on the toolbar.
With the Selection and Smart Drawing Tool, point to some of the used resources within the Fitter assigned LogicLock regions. The names of the signals indicate that the appropriate logic is constrained by the LogicLock regions.
When you are finished looking at the Timing Closure floorplan, choose Close (File menu).
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