ARM-Based Excalibur Module

The ARM^®-based Excalibur^™ device family is based on system-on-a-programmable-chip (SOPC) architecture, consisting of an ARM-based Excalibur embedded processor stripe and an APEX^™ 20KE programmable logic device (PLD). The stripe contains the ARM processor core, peripherals, and a memory subsystem. This architecture allows the stripe and programmable logic device to be optimized for performance, enabling maximum integration and system cost reductions.

This tutorial guides you through the steps necessary to create and instantiate an ARM-based Excalibur processor megafunction in a design, perform a functional simulation in the Quartus II software, build software code to run on the ARM-based Excalibur embedded processor core, and program an Excalibur device.

This tutorial assumes you have installed the Altera ARM Developer Suite (ADS) version 1.1 to the c:\program files\arm\adsv1_1\ directory. If you installed ADS in a different drive and/or directory, substitute the appropriate drive and/or directory name when completing this tutorial. In addition, this Advanced tutorial module assumes that you are familiar with the basic functionality of the Quartus II software, as described in the Basic tutorial modules.

Section 1: Open the arm_tutorial Project

The Excalibur tutorial module uses the Altera-provided arm_tutorial project to teach you how to implement designs for an ARM-based Excalibur device. This project, and its associated files, are installed on your computer during the Quartus II installation process.

To open the arm_tutorial project, follow these steps:

1. Choose Open Project (File menu). The Open Project dialog box appears.

2. In the \qdesigns\excalibur subdirectory, select the Altera-provided arm_tutorial.quartus project file in the File name list.

3. Click Open.

Section 2: Create the ARM-based Excalibur Embedded Processor Megafunction

The stripe portion of the ARM-based Excalibur device contains the ARM processor core, peripherals, and memory subsystem. The dual-port RAM memory and the system bridges support the interface between the stripe and the programmable logic array.

This section describes how to use the MegaWizard^® Plug-In Manager (Tools menu) to create a megafunction variation of the ARM-based Excalibur embedded processor megafunction and instantiate it in the top-level design file, arm_top.bdf. The Mega-Wizard Plug-In Manager allows you to create or modify design files that contain custom variations of megafunctions, such as the ARM-based Excalibur embedded processor megafunction. The ARM-Based Excalibur MegaWizard Plug-In helps you to specify options for the embedded processor stripe easily. Once the ARM-Based Excalibur MegaWizard Plug-In generates the embedded processor stripe, you can instantiate it in the design file.

Step 1: Create the ARM-based Excalibur Processor Megafunction

To use the ARM-Based Excalibur MegaWizard Plug-In, which is available from the MegaWizard Plug-In Manager (Tools menu), to create the ARM-based Excalibur embedded processor megafunction, follow these steps:

1. Choose MegaWizard Plug-In Manager (Tools menu). The first page of the MegaWizard Plug-In Manager appears.






2. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

3. Under Which megafunction would you like to customize?, select ARM-Based Excalibur.

4. Specify the following responses to the remaining wizard prompts:

Wizard Prompt:	Response:
Which device family will you be using?	EXCALIBUR_ARM
Which type of output file do you want to create?	Verilog HDL
What name do you want for the output file?	d:\qdesigns\excalibur\arm_processor.v






5. Click Next. MegaWizard Plug-In Manager - Excalibur [Page 3 of 7] appears.

Step 2: Specify ARM-Based Excalibur Device Options

To specify ARM-based Excalibur device options, follow these steps:

1. In MegaWizard Plug-In Manager - Excalibur page 3, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Select Excalibur family	Make sure Excalibur_ARM is selected.
Select available device	Make sure EPXA10 is selected.
Reset Operation	Make sure both options are turned off.
Byte order	Make sure Little endian is selected.
Reserve pins	Make sure all options are turned off.






2. Click Next. MegaWizard Plug-In Manager - Excalibur [Page 4 of 7] appears.

Step 3: Configure the Interface Between the Stripe & PLD

The PLD-TO-STRIPE and STRIPE-TO-PLD bridges allows the PLD to access resources in the stripe and allows the stripe to access resources in the PLD.

To configure the interface between the stripe and the PLD, follow these steps:

1. In MegaWizard Plug-In Manager - Excalibur page 4, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Bridges	Make sure Do you want to use the STRIPE-TO-PLD bridge (Master Port)? is turned on, and turn off Do you want to use the PLD-TO-STRIPE bridge (Slave Port)?.
Interrupts	Make sure both options are turned off.
Trace / Debug	Make sure Do you want to use processor debug extensions? is turned off.






2. Click Next. MegaWizard Plug-In Manager - Excalibur [Page 5 of 7] appears.

Step 4: Configure the Clocks & SDRAM

To configure the clocks for the stripe, follow these steps:

1. In the MegaWizard Plug-In Manager - Excalibur page 5, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
External clock reference	Enter 50 MHz.
AHB1 / AHB2 clock settings	Make sure Bypass PLL1 is turned on. Make sure 25.00000 MHz is selected in the Select AHB1 frequency list and that 12.50000 MHz is selected in the Select AHB2 frequency list.
Serial Programming	Turn off Are you using a serial EEPROM configuration device?. Make sure 10 is specified in the Enter your programming frequency box.






2. Click Next. MegaWizard Plug-In Manager - Excalibur [Page 6 of 7] appears.

Step 5: Configure Excalibur Memory Mapping

To configure the memory map of the Excalibur device, follow these steps:

1. In MegaWizard Plug-In Manager - Excalibur page 6, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Registers	Make sure 7FFFC000 is specified as the base address and 16K is selected in the size list.
SRAM0	Make sure 00000000 is specified as the base address and 128K is selected in the size list.
SRAM1	Make sure 00020000 is specified as the base address and 128K is selected in the size list.
PLD0	Type 10000000 as the base address and select 16K in the size list. Make sure Prefetch is turned off under PLD0 settings.
Memory map	Make sure all other options are turned off.






2. Click Next. MegaWizard Plug-In Manager - Excalibur [Page 7 of 7] appears. This page lists the files that are created in the project directory for the megafunction.






3. Click Finish to create the ARM-based Excalibur embedded processor megafunction.

Section 3: Instantiate the ARM-Based Excalibur Embedded Processor Megafunction

Once you have created the ARM-based Excalibur embedded processor megafunction, you can then instantiate it in the Altera-provided top-level arm_top.bdf design file and connect it to the other elements of the design. Next, you can perform analysis and elaboration on the design in preparation for performing a bus functional simulation of the design.

Step 1: Open the Top-Level Block Design File

The top-level arm_top Block Design File is installed in the \qdesigns\excalibur directory during the installation process. This file contains the pld_slave logic block that you in turn connect to the Master Port of the arm_processor megafunction. The pld_slave logic block is a slave in the PLD portion of the device that performs addition, subtraction, or multiplication based on the values written to its registers by the Master Port.

To open the arm_top.bdf file:

1. Choose Open (File menu). The Open dialog box appears.

2. In the Files of type list, select Graphic Files.

3. In the \qdesigns\excalibur subdirectory, select the arm_top.bdf file.

4. Click Open.

Step 2: Instantiate the ARM-Based Excalibur Embedded Processor Megafunction

To instantiate the arm_processor symbol generated by the MegaWizard Plug-In Manager in the top-level design, follow these steps:

1. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

2. In the Libraries list, click the + icon to expand the Project list.

3. In the Project list, select the arm_processor symbol. A preview of the newly created arm_processor megafunction appears in the Symbol dialog box.






4. Click OK to instantiate the arm_processor symbol in the BDF. An outline of the arm_processor symbol is attached to the pointer.

5. To place the symbol, click to the right of the clk_ref and npor INPUT pins in the Block Editor window. The arm_processor symbol is instantiated in the BDF as shown in the following illustration.






For simplicity, ports are arranged on the arm_processor symbol according to their stripe function.

Step 3: Connect the Symbol

After instantiating the arm_processor symbol, you must connect the appropriate ports. To connect the ports of the arm_processor symbol to appropriate node and bus lines, position the symbol so that the following connections are made:

Connection from arm_processor Port:	Connect To:
INPUT pin clk_ref	clk_ref input port of arm_processor symbol
INPUT pin npor	npor input port of arm_processor symbol
BIDIR pin nreset	nreset bidirectional port of arm_processor symbol
masterhclk input port of arm_processor symbol	Node line connecting INPUT pin HCLOCK to HCLOCK input port of pld_slave symbol
masterhready input port of arm_processor symbol	HREADY output port of pld_slave symbol
masterhgrant input port of arm_processor symbol	Node line connected to VCC symbol
masterhrdata[31..0] input port of arm_processor symbol	Conduit connecting the HRDATA[31..0] output port of pld_slave symbol to the HRDATA[31..0] output bus
masterhresp[1..0] input port of arm_processor symbol	HRESP[1..0] output port of pld_slave symbol

Connect the Symbol (cont.)

1. Continue to connect the ports of the arm_processor symbol to appropriate node and bus lines, by positioning the symbol so that the following connections are made:

Connection from arm_processor Port:	Connect To:
masterhwrite output port of arm_processor symbol	HWRITE input port of pld_slave symbol
masterhaddr[31..0] output port of arm_processor symbol	HADDRESS[31..0] input port of pld_slave symbol
masterhburst[2..0] output port of arm_processor symbol	HBURST[2..0] input port of pld_slave symbol
masterhsize[1..0] output port of arm_processor symbol	HSIZE[1..0] input port of pld_slave symbol
masterhhtrans[1..0] output port of arm_processor symbol	HTRANS[1..0] input port of pld_slave symbol
masterhwdata[31..0] output port of arm_processor symbol	HWDATA[31..0] input port of pld_slave symbol






2. Choose Save (File menu).

Step 4: Perform Analysis and Elaboration

Before performing a functional simulation of the design, you must perform analysis and elaboration on the design. During analysis and elaboration, the Compiler submits the design to the database builder, which analyzes the design files for syntax and semantic errors, and extrapolates the hierarchy in the instances of each logic block in the design. To perform analysis and elaboration, follow these steps:

1. Choose Start > Start Analysis & Elaboration (Processing menu). The Compiler analyzes the design.

2. When you receive a message indicating that analysis and elaboration was successful, click OK.

Section 4: Perform a Bus Functional Model Functional Simulation

You can perform a functional simulation of an Excalibur design before compilation and synthesis in the Quartus II software. To do this, you must first generate an uPCore Transaction Model Input File (.mbus_in) that describes the embedded processor bus transactions over the Stripe-To-PLD Bridge via the Stripe Master Port. You can then use the Quartus II Simulator, in addition to the bus functional model, to perform a functional simulation of the design and generate an uPCore Transaction Model Output File (.mbus_out) that lists the bus transactions between the PLD and the stripe.

Step 1: Generate the uPCore Transaction Model Input File

An uPCore Transaction Model Input File (with the extension .mbus_in) is used to simulate AMBA AHB bus transactions in order to verify the functionality of slaves implemented in the PLD portion of an ARM-based Excalibur device. The Simulator uses the uPCore Transaction Model Input File data to simulate the interactions between the Stripe-To-PLD bridge and the PLD slave.

To create an uPCore Transaction Model Input File, you must first create a Master Port High-Level Command File (.dat) that describes the read, write, wrapping, and incremental burst operations, as well as busy and idle transactions and periods of idleness that are initiated by the embedded processor core and directed to the PLD. You can then use the exc_bus_translate utility to generate the uPCore Transaction Model Input File that can be processed by the Simulator.

To use the Altera-provided input.dat Master Port High-Level Command File, which is located in the \qdesigns\excalibur directory, to create the uPCore Transaction Model Input File, follow these steps:

1. Open a DOS or UNIX command prompt.

2. To change to the appropriate project subdirectory:

   Type the following commands at a DOS command prompt: d:  cd qdesigns\excalibur

   or

Type the following command at a UNIX command prompt: cd \qdesigns\excalibur

3. To use the exc_bus_translate utility to process the input.dat file and generate the arm_top.mbus_in file, type the following command at the command prompt:

   exc_bus_translate input.dat arm_top.mbus_in 

4. Refer to the following illustration for an excerpt from the generated arm_top.mbus_in file:






5. Close the DOS or UNIX command prompt.

Step 2: Specify Simulator Settings

To specify Simulator settings for performing a functional simulation, follow these steps:

1. Choose Settings (Assignments menu).

2. In the Category list, select General under Simulator Settings. The General page displays the default Simulator general settings created by the Quartus II software when the project was created.






3. In the Category list, select Mode under Simulator Settings.

4. In the Simulation mode list, select Functional. A description of functional simulation appears in the Description field.






5. In the Category list, select Options under Simulator Settings.

6. Make sure Simulation coverage reporting is turned on.

7. In the uPCore Transaction Model File Name box, type arm_top or click Browse (...) to select the arm_top.mbus_in file. The Simulator uses this file to simulate the interactions between the Stripe-To-PLD bridge and the PLD slave.






8. In the Category list, select Time/Vectors under Simulator Settings.

9. Under Simulation period, make sure Run simulation until all vector stimuli are used is selected.

10. Under Vectors, in the Source of vector stimuli box, type D:\qdesigns\excalibur\arm_top.vwf, or click Browse (...) to select the file. The arm_top.vwf file contains the input and output vectors required for functional simulation.

11. Make sure Automatically add pins to simulation output waveforms is turned on.






12. Click OK.

Step 3: Simulate the Design

To run a bus functional model functional simulation, follow these steps:

1. Choose Run Simulation (Processing menu).

The Simulator immediately begins to simulate the arm_top top-level design entity and all of its subordinate design entities, using the arm_top Simulator settings and the arm_top.vwf vector source file. It also generates the uPCore Transaction Model Output File, arm_top.mbus_out, which contains the bus transactions (that is, read and write operations) that occur between the PLD and the Stripe Master Port during simulation.

2. When you receive a message indicating that simulation was successful, click OK to close the message box.

Step 4: View the uPCore Transaction Model Output File

An uPCore Transaction Model Output File (with the extension .mbus_out) is generated by the Simulator when you simulate a design that contains an ARM-based Excalibur embedded processor core and you specified an upCore Transaction Model Input File. This file shows the results of the bus functional model simulation.

The uPCore Transaction Model Output File contains the port names (Master Port or Slave Port), the transaction numbers, the addresses where the data is written, the actual and expected data, the length of data access and the state of the transaction.

To view the arm_top.mbus_out file, follow these steps:

1. Choose Open (File menu).

2. In the Files of type list, select All Files.

3. In the \qdesigns\excalibur\ subdirectoy, select the arm_top.mbus_out file.

4. Click Open.






5. To close the arm_top.mbus_out file, choose Close (File menu).

Section 5: Compile the Design

This section guides you as you compile the design and generate a programmable logic Partial SRAM Object File (.psof). The PSOF is combined with the application software HEX File to generate the appropriate configuration files for the ARM-based Excalibur device.

To compile the arm_top design entity, follow these steps:

1. Choose Start Compilation (Processing menu).

The Compiler immediately begins to compile the arm_top design entity, and all of its subordinate design entities, using the existing arm_top Compiler settings. This compilation may require 15 minutes or more, depending on your system.

2. If you receive a message indicating that compilation was successful and there are no errors or warnings displayed in the Messages window, click OK to close the message box.

   You should correct any errors in your design and recompile it until it is error-free before proceeding with the tutorial. If the Compiler displays any error messages in the Messages window, select the message and choose Locate (right button pop-up menu) to find its source(s), and/or choose Help (right button pop-up menu) to display help on the message.

Section 6: Specify Software Build Settings

This section teaches you how to use the Software Build Settings Wizard (Assignments menu) to specify the software build settings for the design. When you create a new project, the Quartus II software creates two default software build settings called Debug and Release, and uses the Debug software build settings as the current software build settings. You can also modify the existing software build settings by using the Settings command (Assignments menu).

The Quartus II software uses the software build settings you specify to perform a software build to create files for an Excalibur embedded processor core. The Quartus II software uses software source files to create a HEX File. The Quartus II software combines the HEX File and PSOF you created during compilation to generate a SOF. You can then use the resulting SOF, which contains the data for configuring a device, to configure an ARM-based Excalibur device using the Quartus II Programmer.

If you are using the Quartus II software for PCs, or you are using the Quartus II software for UNIX or Linux workstations and you have the ARM Developer Suite installed, proceed to Step 1: Specify the Location of the Software Toolset. If you are using the Quartus II software for UNIX or Linux workstations and you do not have the ARM Developer Suite installed, proceed to Add the Altera-Provided SOF to the Project.

Step 1: Specify the Location of the Software Toolset

To perform the software build, you must have installed the ARM Developer Suite (ADS) software version 1.1. The software toolset setting in the Quartus II software specifies the location of the executables for a C/C++ compiler, assembler, and linker, which the Quartus II software uses when performing a software build.

To specify the location of the software toolset, follow these steps:

1. Choose Settings (Assignments menu).

2. In the Category list, select Toolset Directories under Files & Directories.

3. In the Toolset directories list, select ADS Standard Tools.

4. In the Toolset directory box, type c:\program files\arm\adsv1_1\bin as the path to the ADS directory or click Browse (...) select the directory.

5. Click Change.






6. Click OK.

Step 2: Specify CPU Options

The CPU options of the Software Build Settings Wizard (Assignments menu) allow you to specify the embedded processor core, software toolset, and command-line commands you want the Software Builder to use. The CPU options also allow you to specify the type, name, and byte order of the output file that the Software Builder generates, and whether you want the Software Builder to use an output HEX File with a file that contains PLD configuration data to generate configuration files.

To specify the software toolset and options for the Excalibur embedded processor core, follow these steps:

1. Choose Software Build Settings Wizard (Assignments menu). The Introduction page appears.

2. Click Next. Software Build Settings Wizard: Settings Name [page 1 of 7] appears.

3. Specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Settings name	Select Debug.
Embedded processor architecture	Make sure ARM922T is selected.
Software toolset	Select ADS Standard Tools.






4. Click Next. Software Build Settings Wizard: Byte order and output [page 2b of 7] appears.

5. Specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
What is the byte order?	Make sure Little endian is selected.
Which format do you want the output file to have?	Make sure Hexadecimal (Intel-Format) File (.hex) is selected.
What is the name of the output file?	Make sure Debug\arm_tutorial.hex is specified.
Do you want to run a post-build command line at the end of the software build?	Make sure No is selected.

The Quartus II software automatically places all generated software build files (including arm_tutorial.hex) in a directory with the same name as the current software build settings, that is, Debug.






6. Click Next. Software Build Settings Wizard: Programming File Generation [page 3 of 7] appears.

7. Under Which type of programming file do you wish to create? select the file type for the passive configuration scheme and type arm_top.psof in the File name box.






8. Click Next. Software Build Settings Wizard: C/C++ Compiler [page 4a of 7] appears.

Step 3: Specify C/C++ Compiler Options

The C/C++ compiler options of the Software Build Settings Wizard allow you to specify the optimization level and goal, preprocessor definitions, include directories, and command-line options for a software toolset C/C++ compiler to use during a software build. The C/C++ compiler options also allow you to specify whether you want the C/C++ compiler to ignore standard include directories, generate debug information, or suppress warning during the software build.

To specify the options for the C/C++ compiler, follow these steps:

1. In the Software Build Settings Wizard: C/C++ Compiler page 4a, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
What level of optimization do you want?	Make sure Low is selected.
What is your optimization goal?	Make sure Minimize size is selected.
Do you want to include any preprocessor definitions when the C/C++ compiler is running?	Make sure No is selected.
Do you want the C/C++ compiler to search any additional directories for Include Files (.h)?	Make sure No is selected.
Select additional C/C++ compiler options	Make sure Generate debug information is turned on and Suppress warnings is turned off.






2. Click Next. Software Build Settings Wizard: Assembler [page 5 of 7] appears.

Step 4: Specify Assembler Options

The Assembler options of the Software Build Settings Wizard allow you to specify preprocessor definitions, include directories, and command-line options for a software toolset assembler to use during a software build. These options also allow you to specify whether you want the assembler to generate debug information, keep local symbols, suppress warnings, or use a C preprocessor during a software build.

To specify the Assembler options, follow these steps:

1. In the Software Build Settings Wizard: Assembler page 5, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Do you want to include any preprocessor definitions when the assembler is running?	Make sure No is selected.
Do you want the assembler to search any additional directories for Include Files (.h)?	Make sure No is selected.
Select additional assembler options	Make sure Generate debug information and Keep local symbols in symbol table are turned on and Suppress warnings is turned off.






2. Click Next. Software Build Settings Wizard: Linker [page 6 of 7] appears.

Step 5: Specify Linker Options

The Linker options of the Software Build Settings Wizard allow you to specify the object files, Library Files (.a), library directories, link type, and command-line options for a software toolset linker to use during a software build.

To specify the Linker options, follow these steps:

1. In the Software Build Settings Wizard: Linker page 6, specify the following responses to the wizard prompts:

Wizard Prompt:	Response:
Do you want the linker to ignore the default libraries?	Make sure No is selected.
Do you want the linker to search any additional directories for libraries?	Make sure No is selected.
Do you want to use a 'simple' link or a custom link script?	Make sure Simple is selected. Turn on Entry symbol name/address and specify 0x0 in the box as the address. Turn on Read-only base address and specify 0x0 in the box as the address. Turn on Read/write base address and specify 0x20000 in the box as the address.
Additional command line options	Before the existing commands, add -info totals -map -list arm_tutorial.map -first vectors.o(Vect) .






2. Click Next. Software Build Settings Wizard: Summary [page 7 of 7] appears.






3. Click Finish to close the wizard and save the software build settings

Step 6: Add Software Files to Project

The Quartus II software uses software source files to create a HEX File that contains the memory initialization data. The Quartus II software then uses the HEX File and the PSOF created during compilation to generate passive programming files, including a SOF.

To add the Altera-provided software source files to the project, follow these steps:

1. Choose Add/Remove Files in Project (Project menu). The Add/Remove page of the Settingsdialog box appears.

2. Click Browse (...). The Select File dialog box appears.

3. In the Files of type list, select Software Files.

4. In the \qdesigns\excalibur\arm_c\ subdirectory, select the arm_tutorial.c file.

5. Click Open. The file arm_tutorial.c appears in the File name list.

6. Repeat steps 5 and 6 above to add the following software source files to the project:

File name	Description
init.s	Assembly File (.s) that contains initialization data for arm_tutorial.c.
vector.s	Assembly File that contains initialization data for arm_tutorial.c






7. Click OK. You have now added all the necessary software source files required to run the software build.

Step 7: Perform a Software Build

You can use the Start Software Build command to compile, build and link the software source files. The Quartus II makeprogfile utility then combines the resulting HEX File with the PSOF to create a SOF. You can then use the SOF to configure an ARM-based Excalibur device.

To start the software build, follow these steps:

1. Choose Start Software Build (Processing menu).

2. If you receive a message indicating that the software build was successful and there are no errors displayed in the Messages window, click OK to close the message box.

   You should correct any errors in your design and perform the software build again until it is error-free before proceeding with the tutorial. If the Software Builder displays any error messages in the Messages window, select the message and choose Locate (right button pop-up menu) to find its source(s), and/or choose Help (right button pop-up menu) to display help on the message.

Section 7: Configure the Device

After a successful compilation and software build, the Quartus II software generates one or more programming files that the Programmer can use to program or configure a device. This tutorial section describes downloading configuration data into an ARM-based Excalibur device through the MasterBlaster communication cable.

Before configuring a device, you must open the Programmer and create a Chain Description File (.cdf) that stores device name, device order, and programming and hardware setup information. You can use the CDF to configure an ARM-based Excalibur device in a Passive Serial chain.

Step 1: Open the Programmer Window

To open the Programmer window and create a CDF, follow these steps:

1. Choose New (File menu). The Device Design Files tab of the New dialog box appears automatically.

2. Click the Other Files tab.

3. In the Other Files tab, select Chain Description File.

4. To create the CDF, click OK. The Programmer window opens with a blank CDF.






5. Choose Save As (File menu). The Save As dialog box appears.

6. Type arm_top.cdf in the File name box. In the Save as type list, make sure that Chain Description File is selected.

7. Click Save.

Step 2: Set Up a Passive Serial Chain

To set up configuration for a single device in a Passive Serial chain, follow these steps:

1. In the Mode list of the Programmer window, make sure JTAG is selected.

2. Under Programming Hardware, click Setup. The Hardware Setup dialog box appears.

3. Click Add Hardware. The Add Hardware dialog box appears.

4. In the Hardware Type list, select MasterBlaster and, if necessary, select a port in the Port list.

5. Click OK.

6. In the Hardware Setup dialog box, click Close.

7. Click Add File. The Select Programming File dialog box appears.

8. In the \qdesigns\excalibur\ subdirectory, select the arm_top.sof file.

9. Click Open.

10. In the programming list, turn on Program / Configure.






11. Choose Save (File menu).

If you want to program multiple devices, you can repeat steps 7 through 10 to add additional devices. However, for the purposes of this tutorial, only one programming file is necessary.

Step 3: Start Configuration

To configure the device(s), follow these steps:

1. To program with a MasterBlaster download cable, attach the MasterBlaster cable to an RS-232 cable connected to a serial RS-232 port on the PC or UNIX workstation.

2. Connect the 16-pin female header end of the cable to the 16-pin male MasterBlaster port, and the 10-pin female end of the cable to the 10-pin male header on the target printed circuit board.

3. Click Start in the Programmer window. When you receive a message indicating that the configuration is complete, click OK.

Refer to the Quartus II Installation & Licensing for PCs manual or the Quartus II Installation & Licensing for UNIX and Linux Workstations manual for more information about setting up programming hardware.

If you want to continue to the next tutorial module, proceed to the LogicLock module. If you want to start another tutorial module, return to Start the Tutorial.