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Quartus® II support for behavioral modeling is described below. Section numbers match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.
| Section | Verilog HDL Construct | Quartus II Support Note (1) |
|---|---|---|
| 9.2 | Procedural Assignments | Supported as defined in subsections 9.2.1 and 9.2.2. |
| 9.2.1 | Blocking Procedural Assignments | Supported. |
| 9.2.2 | Nonblocking Procedural Assignments | Supported. |
| 9.3 | Procedural Continuous Assignments | Not supported. |
| 9.3.1 | Assign and Deassign Procedural Continuous Assignments | Not supported. |
| 9.3.2 | Force and Release Procedural Continuous Assignments | Not supported. |
| 9.4 | Null Statements | Supported for all statements except For Statements. |
| 9.4 | Conditional Statements(If-Else Statements) | Supported. |
| 9.5 | Case Statements | Supported. |
| 9.6 | Looping Statements | Supported. |
| 9.7 | Procedural Timing Controls | Supported as defined in subsections 9.7.1 through 9.7.6. |
| 9.7.1 | Delay Controls | Not supported. |
| 9.7.2 | Event Controls | Supported at the top of Always Constructs only. |
| 9.7.3 | Named Events | Not supported. |
| 9.7.4 | Event or Operators |
Supported. |
| 9.7.5 | Level-Sensitive Event Controls (Wait Statements) | Not supported. |
| 9.7.6 | Intra-Assignment Timing Controls | Not supported. |
| 9.8 | Block Statements | Supported as defined in subsections 9.8.1 and 9.8.2. |
| 9.8.1 | Sequential Blocks (Begin-End Blocks) | Supported. |
| 9.8.2 | Parallel Blocks (Fork-Join Blocks) | Not supported. |
| 9.9 | Behavioral Constructs | Supported as defined in subsections 9.9.1 and 9.9.2. |
| 9.9.1 | Initial Constructs | Not supported. Ignored for synthesis. |
| 9.9.2 | Always Constructs | Supported. |
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- Last Modified: 01/05/2003 12:04:54 - |
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