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VHDL

Example of Case Statement

Not recognized as a state machine:

IF state_machine = s0 THEN
   state_machine <= s1;
ELSE
   state_machine <= s2;
END IF;

Recognized as a state machine:

CASE state_machine IS
   WHEN s0=>
      state_machine <= s1;
   WHEN OTHERS =>
      state_machine <= s2;
END CASE;

- PLDWorld -

- Last Modified: 01/05/2003 12:04:46 -

 
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