Megafunction

lpm_tff (T Flipflop) Megafunction

Parameterized T-type flipflop megafunction. Altera® recommends that you use lpm_ff rather than lpm_tff. The lpm_tff megafunction is provided only for backward compatibility.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_tff (data[LPM_WIDTH-1..0], clock, enable, sclr,
      sset, sconst, sload, aclr, aset, aconst, aload)
   WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)
   RETURNS (q[LPM_WIDTH-1..0]);
NOTE The sconst and aconst ports are provided only for backward compatibility, but should be left unconnected in newer projects.

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] Yes Data inputs/bit enables for the T flipflops. Data input during aload or sload. Input port LPM_WIDTH wide.
clock Yes Positive-edge-triggered clock.  
enable No Clock enable input. Enables all synchronous activities. Default is enabled (1).
sclr No Synchronous clear input. Clears the T flipflop on the next active clock edge. Default = 0. If both sset and sclr are used and both are asserted, sclr is dominant.
sset No Synchronous set input. Sets the T flipflop on the next active Clock edge. Default = 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q to all 1's. If both sset and sclr are used and both are asserted, sclr is dominant. The sset signal affects the q[] outputs before polarity is applied.
sload No Synchronous load input. Loads the T-type flipflops with the value on the data input on the next active Clock edge. Default = 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high or unconnected.
aclr No Asynchronous clear input. Default = 0. If both aset and aclr are used and both are asserted, aclr is dominant.
aset No Asynchronous set input. Default = 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is dominant. The sset signal affects the q[] outputs before polarity is applied.
aload No Asynchronous load input. Asynchronously loads the T flipflops with the value on the data input. Default = 0. If aload is used, data must be used.

OUTPUT PORTS

Port Name Required Description Comments
q[] Yes Data output from T flipflops. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] and q[] ports.
LPM_AVALUE Integer / String No Constant value that is loaded when aset is high (1). If omitted, defaults to all 1s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_SVALUE Integer / String No Constant value that is loaded on the rising edge of clock when sset is high (1). If omitted, defaults to all 1s. Altera recommends that you specify this value as a decimal number for AHDL designs.

 

Truth Table/Functionality:
Inputs Outputs
aclr aset aload enable clock sclr sset sload q[LPM_WIDTH-1..0]
1 x x x x x x x 000...
0 1 x x x x x x 111... or LPM_AVALUE
0 0 1 x x x x x data[LPM_WIDTH-1..0]
0 0 0 0 x x x x q[LPM_WIDTH-1..0]
0 0 0 1 Rising Edge 1 x x 000...
0 0 0 1 Rising Edge 0 1 x 111... or LPM_SVALUE
0 0 0 1 Rising Edge 0 0 1 data[LPM_WIDTH-1..0]
0 0 0 1 Rising Edge 0 0 0 q[LPM_WIDTH-1..0]
XOR data[LPM_WIDTH-1..0]

 

Resource Usage:

Uses one logic cell.

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