Megafunction

lpm_latch (Latch) Megafunction

Parameterized latch megafunction. Altera® recommends that you use the lpm_latch function only if the aset port is needed; otherwise, you should use the LATCH primitive rather than lpm_latch for easier implementation and improved compilation time.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_latch (data[LPM_WIDTH-1..0], gate, aclr, aset, aconst)
   WITH (LPM_WIDTH, LPM_AVALUE)
   RETURNS (q[LPM_WIDTH-1..0]);
NOTE The aconst port is provided only for backward compatibility, but should be left unconnected in newer projects.

 

VHDL Component Declaration:

 
COMPONENT lpm_latch
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_AVALUE: STRING := "UNUSED";
      LPM_PVALUE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_LATCH";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      gate: IN STD_LOGIC;
      aclr, aset: IN STD_LOGIC := '0';
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] No Data input to the latch. Input port LPM_WIDTH wide. If the data[] input is not used, then either aset or aclr inputs must be used.
gate Yes Latch enable input. High = flow-through, low = latch.
aclr No Asynchronous clear input. Default = 0. Sets the latch to all 0s. If both aset and aclr are used and both are asserted, aclr is dominant. aset and aclr affect the q[] outputs before the polarity is applied to the ports.
aset No Asynchronous set input. Default = 0. Sets q outputs to the value specified by LPM_AVALUE, if that value is present, or sets the count to all 1s. If both aset and aclr are used and both are asserted, aclr is dominant. aset and aclr affect the q[] outputs before polarity is applied to the ports.

OUTPUT PORTS

Port Name Required Description Comments
q[] Yes Data output from the latch. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] and q[] ports.
LPM_AVALUE Integer / String No Constant value that is loaded when aset is high. If omitted, defaults to all 1s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:
Inputs Outputs
aclr aset gate q[LPM_WIDTH-1..0]
1 x x 000...
0 1 x 111... or LPM_AVALUE
0 0 1 data[LPM_WIDTH-1..0]
0 0 0 q[LPM_WIDTH-1..0]

 

Resource Usage:

Uses a single logic cell per bit.

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