Megafunction

lpm_divide (Divider) Megafunction

Parameterized divider megafunction. Altera® recommends using lpm_divide rather than divide for divider functions. If you need extra features, however, you can use divide. The lpm_divide megafunction takes a numerator and a denominator and computes a quotient and a remainder.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_divide (numer[LPM_WIDTHN-1..0], denom[LPM_WIDTHD-1..0], clock, aclr, clken)
   WITH (LPM_WIDTHN, LPM_WIDTHD, LPM_PIPELINE, LPM_NREPRESENTATION, LPM_DREPRESENTATION, MAXIMIZE_SPEED, LPM_REMAINDERPOSITIVE)
   RETURNS (quotient[LPM_WIDTHN-1..0], remain[LPM_WIDTHD-1..0];

 

VHDL Component Declaration:

 
COMPONENT lpm_divide
   GENERIC ( LPM_WIDTHN: POSITIVE;
      LPM_WIDTHD: POSITIVE;
      --LPM_WIDTHQ: POSITIVE;
      --LPM_WIDTHR: POSITIVE;	    
      LPM_NREPRESENTATION: STRING := "UNSIGNED";
      LPM_DREPRESENTATION: STRING := "UNSIGNED"; 
      LPM_REMAINDERPOSITIVE: STRING := "TRUE"; 	  
      LPM_PIPELINE: INTEGER := 0;
      LPM_TYPE: STRING := "LPM_DIVIDE";
      LPM_HINT: STRING := "UNUSED");
   PORT ( numer: IN STD_LOGIC_VECTOR(LPM_WIDTHN-1 DOWNTO 0);
      denom: IN STD_LOGIC_VECTOR(LPM_WIDTHD-1 DOWNTO 0);
      clock, aclr: IN STD_LOGIC := '0';
      clken: IN STD_LOGIC := '1'; 	  
      quotient: OUT STD_LOGIC_VECTOR(LPM_WIDTHN-1 DOWNTO 0);
      remain: OUT STD_LOGIC_VECTOR(LPM_WIDTHD-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
numer[] Yes Input port LPM_WIDTHN wide.  
denom[] Yes Input port LPM_WIDTHD wide.  
clock No Clock input for pipelined usage. You must connect the clock input if you set LPM_PIPELINE to a value other than 0.
clken No Clock enable for pipelined usage.  
aclr No Asynchronous clear signal. The aclr port may be used at any time to reset the pipeline to all 0s asynchronously to the clock input.

OUTPUT PORTS

Port Name Required Description Comments
quotient[] Yes Output port LPM_WIDTHN wide. You must use either the quotient[] or the remain[] ports.
remain[] Yes Output port LPM_WIDTHD wide. You must use either the quotient[] or the remain[] ports.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTHN Integer Yes Width of the numer[] and quotient[] port.
LPM_WIDTHD Integer Yes Width of the denom[] and remain[] port.
LPM_NREPRESENTATION String No Type of division performed: "SIGNED" or "UNSIGNED". The signed representation for all library of parameterized modules (LPM) megafunctions is two's complement.
LPM_DREPRESENTATION String No Type of division performed: "SIGNED" or "UNSIGNED". The signed representation for all library of parameterized modules (LPM) megafunctions is two's complement.
LPM_REMAINDERPOSITIVE String No Values are "TRUE" or "FALSE". If this parameter is set to "TRUE", then the value of the remain[] port must be greater than or equal to zero. If this parameter is set to "TRUE", then the value of the remain[] port is either zero, or the value is the same sign, either positive or negative, as the value of the numer port. In order to reduce area and improve speed, Altera recommends setting this parameter to "TRUE" in operations where the remainder must be positive or where the remainder is unimportant.
MAXIMIZE_SPEED Integer No Altera-specific parameter. You can specify a value between 0 and 9. If used, the Quartus® II software attempts to optimize a specific instance of the lpm_divide function for speed rather than routability, and overrides the setting of the Optimization Technique option in the Assignment Organizer (Assignments menu). If MAXIMIZE_SPEED is unused, the value of the Optimization Technique option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the Compiler optimizes lpm_divide megafunctions for higher speed using carry chains; if the setting is 5 or less, the Compiler implements the design without carry chains.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the quotient[] and remain[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined). You cannot specify a value for the LPM_PIPELINE parameter that is higher than LPM_WIDTHN.
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files (.vhd).
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".


Truth Table/Functionality:
TRUE
Inputs Outputs
numer[] denom[] quotient[] remain[]
3 3 1 0
3 2 1 1
3 1 3 0
3 0 X X
3 -1 -3 0
3 -2 -1 1
3 -3 -1 0
-3 3 -1 0
-3 2 -2 1
-3 1 -3 0
-3 0 X X
-3 -1 3 0
-3 -2 2 1
-3 -3 1 0


FALSE
Inputs Outputs
numer[] denom quotient[] remain[]
3 3 1 0
3 2 1 1
3 1 3 0
3 0 X X
3 -1 -3 0
3 -2 -1 1
3 -3 -1 0
-3 3 -1 0
-3 2 -1 -1
-3 1 -3 0
-3 0 X X
-3 -1 3 0
-3 -2 1 -1
-3 -3 1 0

 


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