Megafunction

lpm_decode (Decoder) Megafunction

Parameterized decoder megafunction. Altera® recommends using lpm_decode for data input widths less than or equal to 8. In addition, if the project uses only a few sparse outputs of the decoder, Altera recommends using lpm_compare with one input set to a fixed value, instead of lpm_decode.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_decode (data[LPM_WIDTH-1..0], enable, clock, aclr)
   WITH (LPM_WIDTH, LPM_DECODES, LPM_PIPELINE)
   RETURNS (eq[LPM_DECODES-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_decode
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_DECODES: POSITIVE;
      LPM_PIPELINE: INTEGER := 0;
      LPM_TYPE: STRING := "LPM_DECODE";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      aclr, clock: IN STD_LOGIC := '0';
      clken, enable: IN STD_LOGIC := '1';
      eq: OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] Yes Data input. Treated as an unsigned binary encoded number. Input port LPM_WIDTH wide.
enable No Enable. All outputs low when not active. If absent, the default value is active (high).
clock No Clock for pipelined usage. The clock port provides pipelined operation for the lpm_decode function. For LPM_PIPELINE parameter values other than 0 (default value), the clock port must be connected.
clken No Clock enable for pipelined usage. If omitted, the default is 1.
aclr No Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0s asynchronously to the clock signal.

OUTPUT PORTS

Port Name Required Description Comments
eq[] Yes Decoded output. Output port LPM_DECODES wide. If data[] >= LPM_DECODES, all eq[] are 0.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] port, or the input value to be decoded.
LPM_DECODES Integer Yes Number of explicit decoder outputs. LPM_DECODES <= 2 ^ LPM_WIDTH.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the eq[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:
Inputs Outputs
enable data[LPM_WIDTH-1..0] eq[LPM_DECODES-1..0]
0 X 0000...00
1 LPM_DECODES-1 1000...00
1 LPM_DECODES-2 0100...00
... ... ...
1 1 0000...10
1 0 0000...01

The enable input port is optional. When enable is omitted, the decoder is permanently enabled.

 

Resource Usage:

Uses one logic cell per output for up to 16 outputs, and two logic cells per output for more than 16 outputs.

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