Megafunction

lpm_add_sub (Adder/Subtract) Megafunction

Parameterized adder/subtractor megafunction. Altera® recommends using the lpm_add_sub function to replace all other types of adder/subtractor functions.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_add_sub (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],
      add_sub, clock, aclr, clken)
   WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION, ONE_INPUT_IS_CONSTANT,
      LPM_PIPELINE, MAXIMIZE_SPEED, USE_WYS) RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

 

VHDL Component Declaration:

 
COMPONENT lpm_add_sub
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_DIRECTION: STRING := "UNUSED";
      LPM_REPRESENTATION: STRING := "SIGNED";
      LPM_PIPELINE: INTEGER := 0;
      LPM_TYPE: STRING := "LPM_ADD_SUB";
      LPM_HINT: STRING := "UNUSED"
      ONE_INPUT_IS_CONSTANT: STRING := "NO";
      MAXIMIZE_SPEED: INTEGER; 
      USE_WYS: STRING :=	"OFF");
   PORT (dataa, datab: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      aclr, clock, cin: IN STD_LOGIC := '0';
      clken, add_sub: IN STD_LOGIC := '1';
      result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      cout, overflow: OUT STD_LOGIC);
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
cin No Carry-in to the low-order bit. If omitted, the default is 0.
dataa[] Yes Augend/Minuend Input port LPM_WIDTH wide.
datab[] Yes Addend/Subtrahend Input port LPM_WIDTH wide.
add_sub No If the signal is high, the operation = dataa[]+datab[]+cin. If the signal is low, the operation = dataa[]-datab[]+cin-1. If the LPM_DIRECTION parameter is used, add_sub cannot be used. If omitted, the default is "ADD". Altera recommends that you use the LPM_DIRECTION parameter to specify the operation of the lpm_add_sub function, rather than assigning a constant to the add_sub port.
clock No Clock for pipelined usage. The clock port provides pipelined operation for the lpm_add_sub function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.
clken No Clock enable for pipelined usage. If omitted, the default is 1.
aclr No Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal.

OUTPUT PORTS

Port Name Required Description Comments
result[] Yes dataa[]+datab[]+cin or dataa[]-datab[]+cin-1. Output port LPM_WIDTH wide.
cout No Carry-out (borrow-in) of the MSB. Note (4) The cout port has a physical interpretation as the carry-out (borrow-in) of the MSB. The cout port is most meaningful for detecting overflow in "UNSIGNED" operations. The cout port operates in the same manner for "SIGNED" and "UNSIGNED" operations.
overflow No Result exceeds available precision. Note (5) The overflow port has a physical interpretation as the XOR of the carry-in to the MSB with the carry-out of the MSB. overflow is meaningful only when the LPM_REPRESENTATION parameter value is "SIGNED".

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the dataa[],datab[], and result[] ports.
LPM_DIRECTION String No Values are "ADD", "SUB", and "UNUSED". If omitted, the default is "DEFAULT", which directs the parameter to take its value from the add_sub port. The add_sub port cannot be used if LPM_DIRECTION is used. Altera recommends that you use the LPM_DIRECTION parameter to specify the operation of the lpm_add_sub function, rather than assigning a constant to the add_sub port.
LPM_REPRESENTATION String No Type of addition performed: "SIGNED", "UNSIGNED", or "UNUSED". If omitted, the default is "SIGNED". The signed representation for all library of parameterized modules (LPM) megafunctions is two's complement.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.
ONE_INPUT_ IS_CONSTANT String No Altera-specific parameter. Values are "YES", "NO", and "UNUSED". Provides greater optimization if one input is constant. If omitted, the default is "NO".
MAXIMIZE_SPEED Integer No Altera-specific parameter. You can specify a value between 0 and 10. If used, the Quartus® II software attempts to optimize a specific instance of the lpm_add_sub function for speed rather than routability, and overrides the setting of the Optimization Technique option in the Assignment Organizer (Assignments menu). If MAXIMIZE_SPEED is unused, the value of the Optimization Technique option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the Compiler optimizes lpm_add_sub megafunctions for higher speed using carry chains; if the setting is 5 or less, the Compiler implements the design without carry chains. This parameter should be specified for APEX™ II and Mercury™ devices only when the USE_WYS parameter is not used. This parameter should be specified for Cyclone™, Stratix™, and Stratix™ GX devices only when the USE_WYS parameter and the add_sub port are not used.
USE_WYS String No Specifies whether to construct an optimized accumulator with the data from the result[] port that cannot be merged with any other logic. Values are "ON" and "OFF". If omitted, the default is "OFF". For Cyclone, Stratix, and Stratix GX designs, if you turn on the add_sub port, this parameter setting must be "ON". This parameter is available for Cyclone, APEX II, Mercury, Stratix, and Stratix GX devices only.

 

Truth Table/Functionality:
UNSIGNED
Inputs Outputs
add_sub dataa[LPM_WIDTH-1..0] datab[LPM_WIDTH-1..0] cout, result[LPM_WIDTH-1..0] overflow
1 a b a + b + cin cout
0 a b a - b + cin - 1 !cout


SIGNED
Inputs Outputs
add_sub dataa[LPM_WIDTH-1..0] datab[LPM_WIDTH-1..0] cout, sum[LPM_WIDTH-1..0] overflow
1 a b a + b + cin a >= 0 and b >= 0 and
sum < 0
or a < 0 and b < 0 and
sum >= 0
0 a b a - b + cin - 1 a >= 0 and b < 0 and
sum < 0
or a < 0 and b >= 0 and
sum >= 0

 

Resource Usage:

The following table summarizes the resource usage for an lpm_add_sub megafunction used to implement a 16-bit unsigned adder with a carry-in input and a carry-out output. Logic cell usage scales linearly in proportion to adder width.

Design Goals Design Results
Device Family Optimization
APEX™ 20K Routability
  Speed
Width Logic Cells
16 45
16 18

Numbers of shared expanders used are shown in parentheses ( ).

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