Megafunction

altlvds_rx (LVDS) Megafunction

LVDS receiver megafunction. The altlvds_rx megafunction implements a deserialization receiver. LVDS is one of the high-speed I/O interfaces that uses differential signals without a reference voltage. LVDS uses two wires carrying differential values to create a single channel. These wires are connected to two pins on APEX™ 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, Mercury™, Stratix™, and Stratix™ GX devices to create a single differential LVDS channel. The altlvds_rx megafunction uses ClockLock® PLL circuitry for deserialization.

Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altlvds_rx (rx_in[NUMBER_OF_CHANNELS-1..0], rx_inclock, rx_deskew, 
      rx_pll_enable, rx_data_align, rx_cds_ena, rx_reset[NUMBER_OF_CHANNELS-1..0],
      rx_dpll_reset[NUMBER_OF_CHANNELS-1..0], rx_channel_data_align[NUMBER_OF_CHANNELS-1..0],
      rx_coreclk[NUMBER_OF_CHANNELS-1..0], pll_areset)
   WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, REGISTERED_OUTPUT, 
      INCLOCK_BOOST, INCLOCK_PERIOD, CDS_MODE, INTENDED_DEVICE_FAMILY, INPUT_DATA_RATE,  
      INCLOCK_DATA_ALIGNMENT, REGISTERED_DATA_ALIGN_INPUT, COMMON_RX_TX_PLL, ENABLE_DPA_MODE,  
      ENABLE_DPA_FIFO, USE_DPLL_RAWPERROR, USE_CORECLOCK_INPUT, DPLL_LOCK_COUNT, DPLL_LOCK_WINDOW)
   RETURNS (rx_out[DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1..0], rx_outclock, rx_locked, rx_dpa_locked[NUMBER_OF_CHANNELS-1..0]);

 

VHDL Component Declaration:

 
COMPONENT altlvds_rx 
   GENERIC(NUMBER_OF_CHANNELS       : NATURAL;
      DESERIALIZATION_FACTOR        : NATURAL;
      REGISTERED_OUTPUT             : STRING    := "ON";
      INCLOCK_PERIOD                : NATURAL;
      CLOCK_SETTING                 : STRING    := "UNUSED";
      CDS_MODE                      : STRING    := "UNUSED";
      INTENDED_DEVICE_FAMILY        : STRING    := "APEX20KE"
      INPUT_DATA_RATE               : NATURAL   := 0;
      INCLOCK_DATA_ALIGNMENT        : STRING    := "EDGE_ALIGNED";
      REGISTERED_DATA_ALIGN_INPUT   : STRING    := "ON";
      COMMON_RX_TX_PLL              : STRING    := "ON"
      ENABLE_DPA_MODE               : STRING    := "OFF";
      ENABLE_DPA_FIFO               : STRING    := "ON";
      USE_DPLL_RAWPERROR            : STRING    := "OFF";
      USE_CORECLOCK_INPUT           : STRING    := "ON";
      DPLL_LOCK_COUNT               : NATURAL   := 0;
      DPLL_LOCK_WINDOW              : NATURAL   := 0;);	  
   PORT (rx_in: IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
      rx_reset, rx_dpll_reset, rx_channel_data_align, rx_coreclk: 
         IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0) := (OTHERS => '0');
      rx_inclock: IN STD_LOGIC;
      rx_deskew, rx_data_align, pll_areset: IN STD_LOGIC := '0';
      rx_pll_enable: IN STD_LOGIC := '1';
      rx_out: OUT STD_LOGIC_VECTOR(DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
      rx_outclock, rx_locked: OUT STD_LOGIC);
      rx_dpa_locked: OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0) := (OTHERS => '0');;
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY altera_mf
USE altera_mf.altera_mf_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
rx_in[] Yes LVDS input data port. Input port [NUMBER_OF_CHANNELS-1..0] wide. After deserialization, rx_in[n-1] is the first bit received and rx_in[0] is the last bit received for channel one; for channel two, rx_in[2n-1] is the first bit received and rx_in[n] is the last bit received. For more information on bit order, see Application Note 120 (Using LVDS in APEX 20KE Devices). For APEX II devices you can apply the CDS Clock Phase logic option to the input pins that drive the rx_in port.
rx_inclock Yes LVDS reference input clock.  
rx_deskew No Specifies whether to activate calibration mode. For more information on the rx_deskew port, contact the Altera Applications Department. This port is available for APEX 20KE devices only.
rx_cds_ena No Specifies whether to activate calibration mode. This port must be enabled if the CDS_MODE parameter is specified. For more information on the rx_cds_ena port, contact the Altera Applications Department. This port is available for APEX II devices only.
rx_pll_enable No Enable control for the LVDS PLL.  
rx_data_align No Controls byte alignment circuitry. You can register this port using the rx_outclock port. For more information on the rx_data_align port, contact the Altera Applications Department. This port is available for Stratix and Stratix GX devices only.
rx_reset[] No Synchronizes all channels. Input port [NUMBER_OF_CHANNELS-1..0] wide. This port must be connected if the ENABLE_DPA_MODE parameter is turned on. This port is available for Stratix GX devices only.
rx_dpll_reset[] No Asynchronous reset for all channels. Input port [NUMBER_OF_CHANNELS-1..0] wide. This port is available for Stratix GX devices only.
rx_channel_data_align[] No Controls byte alignment circuitry. Input port [NUMBER_OF_CHANNELS-1..0] wide. You can register this port using the rx_outclock port. For more information on the rx_channel_data_align port, contact the Altera Applications Department. This port is available for Stratix GX devices only.
rx_coreclk[] No LVDS reference input clock. Replaces the non-peripheral clock from the PLL. One clock for each channel. Input port [NUMBER_OF_CHANNELS-1..0] wide. This port is available for Stratix GX devices only.
pll_areset No Asynchronously resets all counters to initial values. This port is available for Stratix and Stratix GX devices only.

OUTPUT PORTS

Port Name Required Description Comments
rx_out[] Yes Deserialized data signal. Output port [DESERIALIZATION_FACTOR * NUMBER_OF_CHANNELS-1..0] wide.
rx_outclock No Internal reference clock.  
rx_locked No Gives the status of the LVDS PLL. When the PLL is locked, this signal is VCC. When the PLL fails to lock, this signal is GND.
rx_dpa_locked[] No Indicates whether the channel is locked to dynamic phase alignment (DPA) mode. Output port [NUMBER_OF_CHANNELS-1..0] wide. This port is available for Stratix GX devices only.

 

Parameter Descriptions:
Parameter Type Required Description
NUMBER_OF_CHANNELS Integer Yes Specifies the number of LVDS channels.
DESERIALIZATION_FACTOR Integer Yes Specifies the number of bits per channel. Values are 4, 7, or 8 for APEX 20KE and ARM-based Excalibur devices; 4-10 for APEX II, Stratix, and Stratix GX devices; and 4, 7-12, 14, 16, 18, or 20 for Mercury devices. The value of the INCLOCK_PERIOD parameter is between [125 MHz / DESERIALIZATION_FACTOR] and [1000 MHz / DESERIALIZATION_FACTOR].
REGISTERED_OUTPUT String No Indicates whether the rx_out[] port should be registered. Values are "ON" and "OFF". If omitted, the default is "ON".
INCLOCK_PERIOD Integer Yes Specifies the period or frequency of the rx_inclock port. The default time unit is picoseconds (ps). In AHDL designs only, strings, such as 50.5 MHz, are acceptable.
INCLOCK_BOOST Integer No The effective clock period used to sample output data. Values are 1, 2, and 4-10. This parameter is available for APEX II and Mercury devices only.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard Plug-in Manager to calculate the value for this parameter.
CDS_MODE String No Values are "SINGLE_BIT", "MULTIPLE_BIT", and "UNUSED". If omitted, the default is "UNUSED". When this parameter is set to "SINGLE_BIT", the deskew circuitry will expect a bit pattern like "00001111", which can correct for clock skew up to 50% of one clock edge. When this parameter is set to "MULTIPLE_BIT", the deskew circuitry will expect a pattern like "01010101", which can correct for any clock skew but requires user circuitry to align data. The rx_cds_ena port must be enabled if this parameter is specified. This parameter is available for APEX II devices only.
INPUT_DATA_RATE Integer Yes Specifies the data rate into the PLL. The multiplication value for the PLL is INPUT_DATA_RATE / INCLOCK_PERIOD. This parameter is available for Stratix and Stratix GX devices only.
REGISTERED_DATA_ALIGN_INPUT String No Specifies whether the rx_data_align port is registered. Values are "ON" and "OFF". If omitted, the default is "ON". This parameter is available for Stratix and Stratix GX devices only.
INCLOCK_DATA_ALIGNMENT String Yes Specifies the alignment of input data with respect to the rx_inclock port. Values are "EDGE_ALIGNED", "CENTER_ALIGNED", "45_DEGREES", "135_DEGREES", "180_DEGREES", "235_DEGREES", "270_DEGREES", and "315_DEGREES". If omitted, the default is "EDGE_ALIGNED". This parameter is available for Stratix and Stratix GX devices only.
COMMON_RX_TX_PLL String No Specifies whether the Compiler uses the same PLL for both the LVDS receiver and the LVDS transmitter. Values are "ON" and "OFF". If omitted, the default is "ON". This parameter is available for Stratix and Stratix GX devices only.
ENABLE_DPA_MODE String No Turns on DPA mode. Values are "ON" and "OFF". If omitted, the default is "OFF". This parameter is available for Stratix GX devices only.
ENABLE_DPA_FIFO String No Indicates whether the DPA FIFO buffer is enabled for this channel. Values are "ON" and "OFF". If omitted, the default is "ON". This parameter is available for Stratix GX devices only.
USE_DPLL_RAWPERROR String No Indicates whether the rx_dpa_locked[] port should count or send rawperror, a measure of the parity error when DPA is not turned on. The rx_dpa_locked port must be connected if you turn on this parameter. Values are "ON" and "OFF". If omitted, the default is "OFF". This parameter is available for Stratix GX devices only.
USE_CORECLOCK_INPUT Integer No Indicates whether the rx_coreclk port or the clock from PLL is used as the non-peripheral clock. The rx_coreclk port must be connected if you turn on this parameter. Values are "ON" and "OFF". If omitted, the default is "ON". This parameter is available for Stratix GX devices only.
DPLL_LOCK_COUNT Integer No Specifies the number of clock cycles of rawperror data the rx_dpa_locked port should count. Values are 1, 2, 4, 8, 16, 32, and 64. If omitted, the default is 2. The USE_DPLL_RAWPERROR parameter must be unconnected if you turn on this parameter. This parameter is available for Stratix GX devices only.
DPLL_LOCK_WINDOW Integer No Specifies, in picoseconds (ps), the lock window for the DPLL_LOCK_COUNT parameter. Values are 100, 200, 400, or 800. The DPLL_LOCK_COUNT parameter must be connected if you turn on this parameter. The default values for the parameter vary based on the value of the INPUT_DATA_RATE parameter. This parameter is available for Stratix GX devices only.

INPUT_DATA_RATE DPLL_LOCK_WINDOW
155 Mbps 800 ps
155-311 Mbps 400 ps
312-622 Mbps 200 ps
623-1250 Mbps 100 ps

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