altddio_in (DDIO Input) Megafunction
Double Data Rate (DDR) input megafunction. The altddio_in megafunction receives data on both edges of the reference clock. The altddio_in megafunction is available for APEX II, Cyclone, Mercury, Stratix, and Stratix GX devices only.
This topic contains the following information:
AHDL Function Prototype (port name and order also apply to Verilog HDL):
FUNCTION altddio_in (datain[(WIDTH) - (1)..0], inclock, inclocken, aclr, aset)
   WITH (WIDTH, POWER_UP_HIGH, INTENDED_DEVICE_FAMILY)
   RETURNS (dataout_h[(WIDTH) - (1)..0], dataout_l[(WIDTH) - (1)..0]);
VHDL Component Declaration:
COMPONENT altddio_in
    GENERIC 
       (WIDTH		: POSITIVE	:= 1;
        POWER_UP_HIGH	: STRING  	:= "OFF");
		
    PORT (data_in 		: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
          inclock 		: IN STD_LOGIC;
          in_clocken 		: IN STD_LOGIC := 1; 
          aclr, aset 		: IN STD_LOGIC := 0;
          dataout_h, dataout_l 	: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
END COMPONENT;
Port Descriptions:
INPUT PORTS
  
    | Port Name | 
    Required | 
    Description | 
    Comments | 
  
   
    data_in[] | 
    Yes | 
    DDR input data port. | 
    Input port WIDTH wide. The data_in port should be directly fed from an input pin in the top-level design. | 
  
   
    inclock | 
    Yes | 
    Clock signal to sample the DDR input. | 
    The data_in port is sampled on each clock edge of the inclock signal. | 
  
   
    inclocken | 
    No | 
    Clock enable for the data clock. | 
      | 
  
   
    aclr | 
    No | 
    Asynchronous clear input. | 
    The aclr port and the aset port cannot be connected at the same time. | 
  
 
   
    aset | 
    No | 
    Asynchronous set input. | 
    The aclr port and the aset port cannot be connected at the same time. | 
  
       
OUTPUT PORTS
  
    | Port Name | 
    Required | 
    Description | 
    Comments | 
  
  
   
    dataout_h[] | 
    Yes | 
    Data sampled from the data_in[] port at the rising edge of the inclock signal. | 
      | 
  
  
   
    dataout_l[] | 
    Yes | 
    Data sampled from the data_in[] port at the falling edge of the inclock signal. | 
      | 
  
Parameter Descriptions:
  
    | Parameter | 
    Type | 
    Required | 
    Comments | 
  
  
   
    WIDTH | 
    Integer | 
    Yes | 
    Width of the data_in, dataout_h, and dataout_l ports. | 
  
  
   
    POWER_UP_HIGH | 
    String | 
    No | 
    When both the aset and aclr ports are unused, the POWER_UP_HIGH parameter is available to specify the power-up state of the output ports. Values are "ON", and "OFF". If omitted, the default is "OFF". | 
  
   
    INTENDED_DEVICE_FAMILY | 
    String | 
    No | 
    This parameter is used for modeling and behavioral simulation purposes. Create the altddio_in megafunction with the MegaWizard® Plug-in Manager to calculate the value for this parameter. | 
  
        
  
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