// ********************************************************
// Design : Full Adder                                    *
// Purpose: To be used as an example in the Testbench     *
//          eXtractor [TX] document.                      *
// Author : Venkat Talapaneni                             *
// Date   : October 29, 1997.                             *
// ********************************************************/

`timescale 100ps/1ps

module full_adder(carry_out, sum, carry_in, in2, in1);
   input  in1;         // First Addend 
   input  in2;         // Second Addend
   input  carry_in;    // Input Carry
   output [1:0] sum;   // Sum 
   output carry_out;   // Output Carry

   half_adder H1 (carry, sum[0], in2, in1);
   half_adder H2 (carry_out, sum[1], carry, carry_in);
endmodule

module half_adder(carry, sum, in1, in2);
   input  in1;
   input  in2;
   output carry;
   output sum;

   xor X1 (sum, in1, in2);
   and A1 (carry, in1, in2);
endmodule