-- ---------------------- -- Copyright © Doulos -- DFT Library -- Designer : Tim Pagden -- Opened: 6 Jun 1993 -- ---------------------- -- Architectures: -- 06.06.93 original library ieee; use ieee.std_logic_1164.all; entity fault_circuit_misr is port ( a : in std_ulogic_vector(9 downto 0); y : out std_ulogic_vector(9 downto 0) ); end fault_circuit_misr; architecture original of fault_circuit_misr is signal and_out : std_ulogic_vector(9 downto 0); begin ands: process (a) begin and_out(0) <= a(7) and a(2); -- and_out(1) <= a(0) and a(6); -- faulty... and_out(1) <= '1' and a(6); and_out(2) <= a(1) and a(9); and_out(3) <= a(8) and a(4); and_out(4) <= a(5) and a(3); and_out(5) <= a(8) and a(2); and_out(6) <= a(5) and a(6); and_out(7) <= a(7) and a(9); and_out(8) <= a(0) and a(4); and_out(9) <= a(1) and a(3); end process; ors: process (and_out) begin y(0) <= and_out(0) or and_out(1) or and_out(2) or and_out(3) or and_out(4); y(1) <= and_out(5) or and_out(6) or and_out(7) or and_out(8) or and_out(9); y(2) <= and_out(0) or and_out(2) or and_out(4) or and_out(6) or and_out(8); y(3) <= and_out(1) or and_out(3) or and_out(5) or and_out(7) or and_out(9); y(4) <= and_out(0) or and_out(3) or and_out(6) or and_out(9) or and_out(2); y(5) <= and_out(1) or and_out(8) or and_out(4) or and_out(5) or and_out(7); end process; y(6) <= '0'; y(7) <= '0'; y(8) <= '0'; y(9) <= '0'; end original;