entity sisr_tb is end sisr_tb; library IEEE; library vfp; library DFT; architecture modular of sisr_tb is use IEEE.std_logic_1164.all; use vfp.std_logic_plus.all; use DFT.fault_circuit_cmpt.all; -- use DFT.all; -- p of alias = (2 ** (test_seq - sig_reg'LENGTH)) -1 = 2**(1024-10)-1 = huge! , for L >> R (usual), p(A) =^= 2**(-sig_reg'LENGTH) ----- 2**(1024) huge-10 -- thus here it's 0.1%, ie error coverage = 99.9%, tends to be =^= fault coverage constant period : time := 10 ns; constant half_period : time := period / 2; constant known_good : integer := 166; -- when lfsr_out comes round to 1023 a 2nd time -- = 824 when a(6) = '1' in faulty circuit constant lots : integer := 1024; component sisr port ( serial_in : std_ulogic; clock : std_ulogic; reset : std_ulogic; lfsr_out : out std_ulogic_vector(9 downto 0); signature_out : out std_ulogic_vector(9 downto 0) ); end component; signal clock : std_ulogic; signal reset : std_ulogic; signal lfsr_out : std_ulogic_vector(9 downto 0); signal serial_in : std_ulogic; signal parallel_out : std_ulogic_vector(9 downto 0); signal timebase : integer := 0; -- signal lfsr10_int_sig : integer; -- signal lfsr10_expected_sig : std_ulogic_vector(9 downto 0); -- signal cycle_sig : integer; begin tester: sisr port map (serial_in, clock, reset, lfsr_out, parallel_out); dut: fault_circuit port map (lfsr_out, serial_in); -- suitable design is probably an adder, and select one of the outputs clock_gen: process begin for i in 0 to lots+7 loop clock <= '1'; wait for half_period; clock <= '0'; wait for half_period; timebase <= timebase + 1; end loop; wait; end process; sim_time: process (timebase) begin if timebase = 0 then reset <= '0'; elsif timebase = 2 then reset <= '1'; elsif timebase = 3 then reset <= '0'; end if; if timebase = 1024 then -- 1024 is num of cycles where signature is known -- = 2 ** num_bits ??? -- check parallel_out, is it equal to known good end if; end process; -- process to check ml lfsr sequence against 1023-cycle randomness - looks good process use std.textio.all; use vfp.string_plus.all; use vfp.integer_plus.all; file lfsr_10 : text is in "lfsr_10_table.txt"; variable lfsr10_line : line; variable lfsr10_int : integer; variable lfsr10_is_good : boolean; variable lfsr10_expected : std_ulogic_vector(9 downto 0); -- variable message : line; -- variable message : line; variable cycle : integer := -1; begin wait until reset = '0'; while not endfile(lfsr_10) loop wait on lfsr_out; cycle := cycle + 1; readline(lfsr_10, lfsr10_line); read(lfsr10_line, lfsr10_int, lfsr10_is_good); if to_integer(lfsr_out) /= lfsr10_int then -- message1 := "In cycle " & cycle; -- message2 := ", lfsr_reg is " & to_string(lfsr_out); -- message3 := ", it should be " & lfsr10_expected; -- write(); -- message := & & -- assert FALSE -- report "lfsr_out is " & to_integer(lfsr_out) -- severity NOTE; -- assert FALSE -- report "lfsr10_expected is " & lfsr10_int -- severity NOTE; -- assert FALSE -- report to_string(lfsr_out) -- severity NOTE; assert FALSE report (("lfsr_out not the same as lfsr10_int ... " & lfsr10_int) & " ... ") & to_string(lfsr_out) -- cycle + 0 is a goddamnawful trick to create an expression from a signal - yeeuuch! severity NOTE; end if; -- lfsr10_int_sig <= lfsr10_int; -- lfsr10_expected_sig <= lfsr10_expected; -- cycle_sig <= cycle; if timebase = 1026 then if to_integer(parallel_out) /= known_good then assert FALSE report "Ooo-er!" severity note; else assert FALSE report "Mmmm, darling! You are sooooo good." severity note; end if; end if; end loop; wait; end process; end modular;