library IEEE; use IEEE.std_logic_1164.all; entity maximal_length_lfsr is port ( clock : std_ulogic; reset : std_ulogic; data_out : out std_ulogic_vector(9 downto 0) ); end maximal_length_lfsr; architecture modular of maximal_length_lfsr is signal lfsr_reg : std_ulogic_vector(9 downto 0); -- consider writing a tip on how to use generates to implement only the taps -- required from a generic rather than implementing a full-blown NSL block -- for all possible tap combos - which is what you get in a process - prove -- or disprove signal cycle : integer := -1; begin process (clock) variable lfsr_tap : std_ulogic; begin if clock'EVENT and clock='1' then if reset = '1' then lfsr_reg <= (others => '1'); else lfsr_tap := lfsr_reg(6) xor lfsr_reg(9); lfsr_reg <= lfsr_reg(8 downto 0) & lfsr_tap; end if; end if; end process; data_out <= lfsr_reg; end modular;