-- ---------------------- -- Copyright © Doulos -- Cell Library -- Designer : Tim Pagden -- Opened: 6 Jun 1993 -- ---------------------- -- Architectures: -- 06.06.93 original library ieee; use ieee.std_logic_1164.all; entity fault_circuit is port ( a : in std_ulogic_vector(9 downto 0); y : out std_ulogic ); end fault_circuit; architecture original of fault_circuit is begin -- p0: process (a, b, c_in) -- begin -- y <= a xor b xor c_in; -- end process; p1: process (a) begin y <= (a(7) and a(2)) or (a(0) and a(6)) or (a(1) and a(9)) or (a(8) and a(4)) or (a(5) and a(3)); end process; -- '1' end original;