-- +-----------------------------+ -- | Copyright 1996 DOULOS | -- | Library: arithmetic | -- | designer : Tim Pagden | -- | opened: 26 Jul 1996 | -- +-----------------------------+ -- Architectures: -- 26.07.96 low_level library arithmetic; architecture low_level of cla_14 is use arithmetic.cla_2_cmpt.all; use arithmetic.cla_3_cmpt.all; use arithmetic.cla_4_cmpt.all; use arithmetic.cla_5_cmpt.all; signal p0, g0, c_0 : std_ulogic_vector(1 downto 0); signal p1, g1, c_1 : std_ulogic_vector(2 downto 0); signal p2, g2, c_2 : std_ulogic_vector(3 downto 0); signal p3, g3, c_3 : std_ulogic_vector(4 downto 0); signal c3, c7, c11, c15 : std_ulogic; signal p_0_0, g_0_0 : std_ulogic; signal p_0_1, g_0_1 : std_ulogic; signal p_0_2, g_0_2 : std_ulogic; signal p_0_3, g_0_3 : std_ulogic; signal p_0, g_0 : std_ulogic_vector(3 downto 0); begin p0 <= p(1 downto 0); g0 <= g(1 downto 0); p1 <= p(4 downto 2); g1 <= g(4 downto 2); p2 <= p(8 downto 5); g2 <= g(8 downto 5); p3 <= p(13 downto 9); g3 <= g(13 downto 9); p_0 <= p_0_3 & p_0_2 & p_0_1 & p_0_0; g_0 <= g_0_3 & g_0_2 & g_0_1 & g_0_0; c <= c_3 & c_2 & c_1 & c_0; -- 0th rank, a set of 4 different width cla cells i0_0: cla_2 port map ( c_in => c_in, p => p0, g => g0, c => c_0, p_out => p_0_0, g_out => g_0_0 ); i0_1: cla_3 port map ( c_in => c3, p => p1, g => g1, c => c_1, p_out => p_0_1, g_out => g_0_1 ); i0_2: cla_4 port map ( c_in => c7, p => p2, g => g2, c => c_2, p_out => p_0_2, g_out => g_0_2 ); i0_3: cla_5 port map ( c_in => c11, p => p3, g => g3, c => c_3, p_out => p_0_3, g_out => g_0_3 ); -- 1st rank, a single cla cell i1_0: cla_4 port map ( c_in => c_in, p => p_0, g => g_0, c(0) => c3, c(1) => c7, c(2) => c11, c(3) => c15, p_out => p_out, g_out => g_out ); end low_level;