-- +-----------------------------+ -- << >>
-- |    designer : Tim Pagden    |
-- |     opened: 30 Sep 1993     |
-- +-----------------------------+
 
-- Architectures:
--   30.09.93 original    ANALYSIS PASSED
--   19.11.94 behavioural 
 
library ieee;
library arithmetic;
library FF;
library vfp;
 
architecture original of FIR_32tap_8_8 is -- << >>
  use ieee.std_logic_1164.all;
  use arithmetic.mult_para_recurs_8x8_2sC_cmpt.all;
  use arithmetic.adder_21_cmpt.all;
  use FF.dff_8_cmpt.all;
  use FF.dff_21_cmpt.all;
--  use vfp.standard_types.all;
  use vfp.bus_class.all;

  constant word_msb_index: integer := 15;

  signal data_bus: std_ulogic_vector(7 downto 0);
  signal coeff_array: ulogic_8_vector(31 downto 0);
  signal product: ulogic_16_vector(31 downto 0);
  signal sum: ulogic_21_vector(31 downto 0);
  signal FIR_tap: ulogic_21_vector(30 downto 0);
  signal lo: std_ulogic;
  signal product_msb: std_ulogic_vector(31 downto 0);
  signal adder_in: ulogic_21_vector(31 downto 0);
 
begin
 
  i3: dff_8
  port map (
    d     => a,
    clock => clock,                                                             
    q     => data_bus
  );

  G0: for i in 0 to 31 generate -- << >>
    i0: multiplier_parallel_recursive_8x8_2sC
    port map (
      a => data_bus,
      b => coeff_array(i),
      clock => clock,
      reset => reset,
      y => product(i)
    );
  end generate;
 
  G1: for i in 1 to 31 generate -- << >>
    i2: product_msb(i) <= product(i)(word_msb_index);
    i0: adder_in(i) <= product_msb(i) & product_msb(i) & product_msb(i) & 
                       product_msb(i) & product_msb(i) & product(i);
    i1: adder_21
    port map (
      a     => adder_in(i),
      b     => FIR_tap(i-1),
      c_in  => lo,
      y     => sum(i),
      c_out => open
    );
  end generate;
 
  G2: for i in 0 to 30 generate
    i2: dff_21
    port map (
      d     => sum(i),
      clock => clock,
      q     => FIR_tap(i)
    );
  end generate;

  -- s0: sum(0) <= "00000" & product(0);
  s0: product_msb(0) <= product(0)(word_msb_index);
  s1: sum(0) <= product_msb(0) & product_msb(0) & product_msb(0) & 
                product_msb(0) & product_msb(0) & product(0);
  s2: y <= sum(31);
  s3: lo <= '0';

  -- data_latch: process (clock)
  --   variable clock_counter: integer;
  -- begin
  --   if (clock = '1' and clock'event) then
  --     if (reset = '0') then
  --       clock_data_in <= '0';
  --     elsif (clock_counter = 32) then
  --       clock_data_in <= not clock_data_in;
  --     end if; 			   
  --     if (reset = '0') then
		-- 		    clock_counter := 0;
  --     else
  --       clock_counter := clock_counter + 1;
  --     end if;     
  --   end if;     
  -- end process;  

end original;

library maths;
library matrix;
library vfp;
library dsp;

architecture behavioural of FIR_32tap_8_8 is
  use maths.maths_class.all;
  use matrix.matrix_class.all;
  use vfp.generic_functions.all;
  use vfp.generic_conversions.all;
  use vfp.mixed_operators.all;
  use vfp.twos_complement_types.all;

  constant number_of_taps: integer := 32;

  signal data_table: single_vector(number_of_taps-1 downto 0);
  signal coefficient_table: single_vector(number_of_taps-1 downto 0);

begin

  -- y <= sum_over (0, k-1, a((k-1)-i), b(i))
  -- coefficient_table <= b;

  fir_algorithm: process (clock)
    variable data_out : single;
    variable fir_result : single;
    variable data_table_var: single_vector(number_of_taps-1 downto 0);
    -- the coeff table assignment really ought to be handled at the entity interface
    variable coefficient_table_var: single_vector(number_of_taps-1 downto 0);
    variable tmp : single_vector(number_of_taps-1 downto 0);
    variable tmp2 : single;
    variable tmp3 : single_vector(number_of_taps-1 downto 0);
    variable tmp4 : integer;
    variable num_taps_minus_1 : integer;
    variable y_result : twos_complement(20 downto 0);
  begin
    if posedge (clock) then
      -- data_table_var := data_table(number_of_taps-1) & data_table(number_of_taps-2 downto 0);
      -- putting the coeff table in a loop like this allows dynamic coeff updating
      for i in 0 to number_of_taps-1 loop
        coefficient_table_var(i) := single(to_integer(b(i)))/127.0;
      end loop;
      -- tmp := reverse_order(data_table_var);
      
      -- tmp2 := 0.15;  + to_integer(a);
      data_table_var := data_table;
      tmp2 := single(to_integer(to_twos_complement(a)));
      data_table_var := shift_fifo (data_table_var, tmp2); -- fifo =>  data_in => 
      data_table <= data_table_var;

      -- tmp3 := reverse_order(data_table_var);
      -- tmp4 := 0;
      num_taps_minus_1 := number_of_taps-1;
      fir_result := sum_of_products (
        lower_limit => 0,
        upper_limit => number_of_taps-1,
        a_in => reverse_order(data_table_var),
        b_in => coefficient_table_var
      );
      y_result := y_result = integer(fir_result); -- this causes an array bug to_std_ulogic_vector(
      y <= to_std_ulogic_vector(y_result); -- this causes an array bug  -- to_twos_complement
    end if;
  end process;
  
end behavioural;
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