-- +-----------------------------+
-- | Copyright 1995-1996 DOULOS  |
-- |       Library: memory       |
-- |    designer : Tim Pagden    |
-- |     opened: 26 Nov 1995     |
-- +-----------------------------+

-- Function: generic SRAM model with separate I/O. OE and CS are active HIGH
--   WE latches data on rising edge

library ieee;  
library vfp;
  use ieee.std_logic_1164.all;
  use vfp.generic_functions.all;

entity sram_core_GENERIC is
generic (
  -- entity parameterization (must have these in the generic map)
  address_width : integer := 0; --
  data_width    : integer := 0; -- 
  -- more to do with attribute'ing
  architecture_DNH_filename : string := "????????.dnh" -- 
);              
port (
  address  : in  std_ulogic_vector(address_width-1 downto 0);
  CS       : in  std_ulogic;
  WE       : in  std_ulogic;
  OE       : in  std_ulogic;
  data_in  : in  std_logic_vector(data_width-1 downto 0);
  data_out : out std_logic_vector(data_width-1 downto 0)
);
begin
  -- data bus width must be integer power of 2 bits, < 64
  assert is_factor_of_32(data_width)
    report "Width of data bus must be 1, 2, 4, 8, 16 or 32 bits."
    severity warning;
end sram_core_GENERIC;


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