entity sram_core_GENERIC_tb is
end sram_core_GENERIC_tb;

library IEEE;
library memory;
library vfp;

architecture tb0 of sram_core_GENERIC_tb is
  use IEEE.std_logic_1164.all;
  use vfp.generic_conversions.all;
  use memory.sram_core_GENERIC_cmpt.all;

  constant address_width : integer := 8;
  constant data_width : integer := 8;
  
  signal Addr : std_ulogic_vector(address_width-1 downto 0);
  signal Data : std_logic_vector(data_width-1 downto 0);
  signal Data_out : std_logic_vector(data_width-1 downto 0);
  signal Cs, Oe, We : std_ulogic;
  signal Cs_inv, Oe_inv, We_inv : std_ulogic;

begin
  
  process
    variable loop_index : integer;
    variable addr_signed : std_ulogic_vector(address_width downto 0);
  begin
    We <= '1';
    Cs <= '1';
    Oe <= '1';
    Addr <= (others => '0');
    Data <= (others => 'Z');
    wait for 10 NS;

--  Check out control lines

--  Read with chip disabled
 
    Oe <= '0';
    wait for 10 NS;
    Oe <= '1';
    wait for 10 NS;

--  Read undefined with chip enabled

    Cs <= '0';
    wait for 10 NS;
    Oe <= '0';
    wait for 10 NS;
    Oe <= '1';
    wait for 10 NS;

--  Write with chip disabled

    Data <= (others => '1');
    wait for 10 NS;
    Cs <= '1';
    wait for 10 NS;
    We <= '0';
    wait for 10 NS;
    We <= '1';
    wait for 10 NS;

-- Check nothing was written

    Data <= (others => 'Z');
    wait for 10 NS;
    Cs <= '0';
    wait for 10 NS;
    Oe <= '0';
    wait for 10 NS;
    Oe <= '1';
    wait for 10 NS;

--  Write with chip enabled

    Data <= (others => '1');
    wait for 10 NS;
    Cs <= '0';
    wait for 10 NS;
    We <= '0';
    wait for 10 NS;
    We <= '1';
    wait for 10 NS;

-- Check something was written

    Data <= (others => 'Z');
    wait for 10 NS;
    Oe <= '0';
    wait for 10 NS;
    Oe <= '1';
    wait for 10 NS;

-- Read and write together...

    Data <= (others => '0');
    wait for 10 NS;
    We <= '0';
    Oe <= '0';
    wait for 10 NS;
    We <= '1';
    Oe <= '1';
    wait for 10 NS;


--  Write into all the Ram contents by driving the data bus

    Cs <= '0';
    for i in 0 to 15 loop
      loop_index := i;
      addr_signed := to_std_ulogic_vector (loop_index, address_width+1);
      Addr <= addr_signed(address_width-1 downto 0);
      wait for 5 NS;
      Data <= to_stdlogicvector (Addr);
      wait for 5 NS;
      We <= '0';
      wait for 20 NS;
      We <= '1';
      wait for 20 NS;
    end loop;

--  Turn off driver to the data bus and read out new Ram contents

    Data <= (others => 'Z');
    wait for 50 NS;
    for i in 0 to 15 loop
      loop_index := i;
      addr_signed := to_std_ulogic_vector (loop_index, address_width+1);
      Addr <= addr_signed(address_width-1 downto 0);
      wait for 10 NS;
      Oe <= '0';
      wait for 20 NS;
      Oe <= '1';
      wait for 20 NS;
    end loop;

    wait;
  end process;

  cs_inv <= not cs;
  we_inv <= we;
  oe_inv <= not oe;
  
  G1: sram_core_GENERIC 
    generic map (
      address_width => address_width,
      data_width => data_width
    )
    port map (Addr, Cs_inv, We_inv, Oe_inv, Data, Data_out);

end tb0; 

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