Processor Models

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RASSP Processor Modeling Effort at Georgia Institute of Technology
Point of Contact: Dr. Vijay Madisetti
Form to request information on licensing GTRC models
Processor Architectures
General Taxonomy Level : Behavioral, Full Functional
Created by : Georgia Institute of Technology/ Digital Signal Processing Laboratory

Synthesizable DLX: Generic 32-bit RISC Processor
as part of a complete VLSI Design Course
Description : Based on Hennessy & Patterson's generic 32-bit RISC
Processor Architecture, Synthesizable on Synopsys version 3.2a
General Taxonomy Level : RTL/Structural Version
Created by : University of Stuttgart / Department of Computer Science

DLX: Generic 32-bit RISC Processor -- Copyright (C) 1993, Peter J. Ashenden
or On-line archive
Description : Hennessy & Patterson's generic 32-bit RISC Processor
Architecture
General Taxonomy Level : Behavioral and RTL Versions
Created by : Peter J. Ashenden (petera@cs.adelaide.edu.au)

Alternate DLX: Generic 32-bit RISC Processor -- a compressed tar file
Description : Hennessy & Patterson's generic 32-bit RISC Processor
Architecture
General Taxonomy Level : Behavioral Versions
Created by : Avaneendra Gupta, Paul R. Stephan

GL85: i8085 microprocessor clone (Behavioral and Structural compressed)
behavioral only -- An On-line Archive
RTL only -- An On-line Archive
structural only -- An On-line Archive
documentation -- An On-line Archive
test vector responses -- An On-line Archive
Description : op-code (but not pin compatible) clone of the i8085
microprocessor
General Taxonomy Level : Behavioral and structural models
Created by : Alexander Miczo (alex@attest.com) Attest Software, Inc.

i80386 Microprocessor -- Copyright (C) Convergent, Inc. 1988
Description : Incomplete i80386 processor model
General Taxonomy Level : Behavioral
Created by : Mark Dakur

M68000 microprocessor -- VHDL file
Description : M68000 microprocessor model
General Taxonomy Level : Behavioral
Created by : Ric Heishman, Dave Hollinden, John Krautheim, Tim McBrayer
and Praveen Sinha (University of Cincinnati)

AMD 2901 -- a compressed tar file
Description : AMD 2901 4-bit microprocessor slice
General Taxonomy Level : Behavioral and Structural
Created by : Champaka Ramachandran (champaka@balboa.eng.uci.edu)
Univ. of Cal.,Irvine,

AMD 2910 -- a compressed tar file
Description : AMD 2910 bit slice
General Taxonomy Level : Dataflow and Structural
Created by : Champaka Ramachandran (champaka@balboa.eng.uci.edu)
Univ. of Cal.,Irvine,

ERC32 processor model
Description : ERC32 is a radiation-tolerant SPARC V7 processor developed for space applications.
General Taxonomy Level : Fully functional, timing accurate
Created by : European Space Agency
Additional Information about the model

DP32
Description : DP32 processor model used in the VHDL cookbook
General Taxonomy Level : Behavioral
Created by :

Z80 -- a compressed tar file
Description : Testbench and parser for test patterns that were
generated by the Sentry test, this is not a Z80 model, but can
be used as a testbench for it.
General Taxonomy Level : Behavioral
Created by : M. Markowitz ( EDN Magazine )
W. Billowitch ( VHDL Technology Group )

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