The Designer's Guide to VHDL
Peter J. Ashenden
Source Code and Test Benches
The source code and test benches for examples are available on this server. There is a separate
directory for each chapter, listed below. Each directory contains an index file, called index_nn,
that lists the VHDL design units contained in each source file. (The digits nn are the number
of the chapter.) The source files for most chapters are named as follows:
- ch_nn_xx.vhd contains code from an example embedded in the book text.
- fg_nn_xx.vhd contains code from Figure nn-xx.
- pk_nn_xx.vhd contains a package of declarations used in an example or test bench.
- tb_nn_xx.vhd contains a test bench design unit.
The exceptions to this naming scheme are the files for the case study chapters (Chapters 6, 10,
15 and 19), since some of the design units are divided across several figures in the book. For
these chapters, the files names are based on the names of the design units.
Each chapter directory also contains two archives of all of the source files for that chapter, one
in ZIP format for PC users and the other in compressed tar format for Unix users.
In addition to the source for each chapter, there is a utilities directory, containing a test generator
utility package. Several of the test benches use procedure in this package to generate test stimuli.
The source code has all been tested using the Model Technology Inc V-System/Workstation
analyzer and simulator. I am most grateful to the people at MTI for the use of the tools and for
their support.
If you have comments, please send me email at petera@cs.adelaide.edu.au. Thanks.
1 Fundamental Concepts
2 Scalar Data and Operations
3 Sequential Statements
4 Composite Data Types and Operations
5 Basic Modeling Constructs
6 Case Study: A Pipelined Multiplier Accumulator
7 Subprograms
8 Packages and Use Clauses
9 Aliases
10 Case Study: A Bit Vector Arithmetic Package
11 Resolved Signals
12 Generic Constants
13 Components and Configurations
14 Generate Statements
15 Case Study: The DLX Computer System
16 Guards and Blocks
17 Access Types and Abstract Data Types
18 Files and Input/Output
19 Case Study: Queuing Networks
20 Attributes and Groups
21 Miscellaneous Topics
A Synthesis
Utilities
vhdl/models/misc/ASHENDEN_BOOK/DG-source-code.html