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Legal issues

This site contains VHDL source code written by Doulos staff. You are welcome
to use the source code we provide but you must keep the copyright notice
with the code. If you modify our code for your own requirements, it would be
polite to acknowledge Doulos as the source of the original code in your own
code with a VHDL comment to that effect. For example,

  -- Original VHDL source code Copyright 1995-1996 Doulos
  -- Modified by your name here

When using our code as the starting point or inspiration for your own code
developements, or when you substantially alter our code so that it no longer
reflects the functionality or structure of our original code, you do not
need an acknowledgement comment to Doulos in your VHDL code. However, we
would be more than happy to have you e-mail us your code for inclusion in
our Tip of the Month or Model of the Month pages. Naturally, full
accreditation will be given to you.

Any mention of specific organizations or their products does not imply an
endorsement by Doulos of either the organisation or the product.

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Trademarks

Verilog is a registered trademark of Cadence Design Systems.
Synopsys is a registered trademark of Synopsys Inc.

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Acknowledgements

Page Concept for:
Your VHDL Problems Answered
John Aynsley

Page Concepts for:
Doulos Training Courses
VHDL PaceMaker
ASIC Design Services
Project Services
Rob Hurley

Remaining Page Concepts and Page Design:
Tim Pagden

These pages were not developed using fancy HTML editors! We used Paint Shop
Pro v3.11 for manipulating the images and making the icons. Thanks to
everyone who has taken the time to publish HTML How To's on the Web, we used
these extensively to learn how to code up and design Web pages. The Page
Chronology and Hierarchical Index pages are built using our own in-house
tools.

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 [x]   Doulos Home Page

Copyright 1995-1996 Doulos
This page was last updated 16th February 1996.

We welcome your e-mail comments. Please contact us at:
info@doulos.co.uk

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