------------------------------------------------------------------------------
---                                                                        ---
---            Copyright (c) Abstract Hardware Limited 1996                ---
---                                                                        ---
------------------------------------------------------------------------------

----
- $Id: grey2.vhd,v 1.2 1996/01/30 15:15:21 mikea Exp $
- 
- $Log: grey2.vhd,v $
- Revision 1.2  1996/01/30  15:15:21  mikea
- Changed spelling of grey (code) to gray (code).
-
- Revision 1.1  1996/01/18  11:10:59  mikea
- Initial revision
-
----
-- grey2.vhd Grey Coded VHDL Example
-- VHDL Description of the Second Gray Coded State Machine

------------------------------------------------------------------------
-- CHECKOFF EXAMPLE: Transmitter Control
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
-- Date:   Wed Aug 7 1995
--
-- Copyright (c) Abstract Hardware Limited 1995
------------------------------------------------------------------------


-----------------------------------------------------------------------
-- Transmit Controller Interface
--
--	Entity: 	tx_con
-----------------------------------------------------------------------
entity tx_con is
  port (clk, reset 				    : in  BIT;
        data_rdy, bus_rdy, msg_end 		    : in  BOOLEAN;
        req_bus, xt_data, xt_parity, xt_eow, xt_eom : out BOOLEAN);
end tx_con;


-----------------------------------------------------------------------
-- Package for count constants
--
--	Package:	count_constants
-----------------------------------------------------------------------
package count_constants is
  constant RESET_COUNT   : NATURAL := 0;
  constant SENDING_BIT_2 : NATURAL := 1;
  constant SENDING_BIT_3 : NATURAL := 2;
  constant SENDING_BIT_4 : NATURAL := 3;
end count_constants;

-----------------------------------------------------------------------
-- Transmit Controller - Gray Coded FSM (2 extra states)
--
--	Architecture:	gray_code2
--	Entity: 	tx_con
-----------------------------------------------------------------------
use work.count_constants.all;
architecture gray_code2 of tx_con is

  -- state variables (FSM and Counter)
  signal fsm   : BIT_VECTOR(2 downto 0);
  signal count : NATURAL range 0 to 3;

begin

  ---------------------------------------------------------------------
  -- Combinational logic 
  ---------------------------------------------------------------------
  SET_STATE:
  process (clk)
  begin

    -------------------------------------------------------------------
    -- State function
    -------------------------------------------------------------------
    if (clk'event and clk='1') then
      if reset='1' then 
        fsm <= "000"; -- Idle
      else
	case fsm is
	  when "000" => if data_rdy then
			  fsm <= "100"; -- Idle -> BusReq
			end if;
  
	  when "100" => if bus_rdy then
			  fsm <= "101"; -- BusReq -> TxData
			end if;
  
	  when "101" => if count = SENDING_BIT_4 then
			  fsm <= "111"; -- TxData -> TxParity
			end if;
  
	  when "111" => if msg_end then
			  fsm <= "110"; -- TxParity -> TxEOM
			else
			  fsm <= "011"; -- TxParity -> TxEOW
			end if;
  
	  when "011" => if count = SENDING_BIT_2 then
			  fsm <= "001"; -- TxEOW -> TxEOW_b
			end if;
  
	  -- Extra state to preserve gray coding (TxEOW_b)
	  when "001" => fsm <= "101"; -- TxEOW_b -> TxData
  
	  when "110" => if count = SENDING_BIT_2 then
			  fsm <= "010"; -- TxEOM -> TxEOM_b
			end if;
  
	  -- Extra state to preserve gray coding (TxEOM_b)
	  when "010" => fsm <= "000"; -- TxEOM_b -> Idle
	end case;
      end if;
    end if;


    -------------------------------------------------------------------
    -- Count function
    -------------------------------------------------------------------
    if (clk'event and clk='1') then
      if reset='1' then 
        count <= RESET_COUNT;
      else
	case fsm is
	  when "000" => count <= RESET_COUNT;
  
	  when "100" => count <= RESET_COUNT;
  
	  when "101" => if count = SENDING_BIT_4 then
			  count <= RESET_COUNT;
			else
			  count <= count + 1;
			end if;
  
	  when "111" => count <= RESET_COUNT;
  
	  -- Simplified due to reset in TxEOW_b
	  when "011" => count <= count + 1;
  
	  -- TxEOW_b (extra state)     
	  when "001" => count <= RESET_COUNT; -- for TxData
  
	  when "110" => count <= count + 1;
  
	  -- TxEOM_b (extra state)      
	  when "010" => count <= RESET_COUNT;
	end case;
      end if;
    end if;

  end process SET_STATE;


  ---------------------------------------------------------------------
  -- OUTPUTS 
  ---------------------------------------------------------------------
  SET_OUTPUTS:
  process (fsm)
  begin
    req_bus   <= fsm = "100"; -- BusReq
    xt_data   <= fsm = "101"; -- TxData
    xt_parity <= fsm = "111"; -- TxParity
    
    -- xt_eow extended to cover both TxEOW & TxEOW_b
    case fsm is when "011" | "001" => xt_eow <= true;
 		when others        => xt_eow <= false;
    end case;
    
    -- xt_eom extended to cover both TxEOM & TxEOM_b
    case fsm is when "110" | "010" => xt_eom <= true;
		when others        => xt_eom <= false;
    end case;
  end process SET_OUTPUTS;

end gray_code2;

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