Register files are generally fast RAMS with multiple read and write ports. In Memory Builder,to build a register file you need to specify two parameters for the size of the register file, word (the number of the words) and bpw(bits per word). The assembled register file layout has following terminals.
word
bpw
The register file can have three kinds of operations:
Before you use this model, you need to download utilities & IEEE packages from MPL VHDL Model Collection . This model has been tested successful on Mentor Quick VHDL. You can compile the downloaded VHDL model and simulate.
Click to download the VHDL model.
Any comments and problems? Please feel free to send mail to reese@erc.msstate.edu.